e82ddd28e3
The current DevX implementation of the relaxed ordering feature is
enabling relaxed ordering usage only if both relaxed ordering read AND
write are supported. In that case both relaxed ordering read and write
are activated.
This commit will optimize the usage of relaxed ordering by enabling it
when the read OR write features are supported. Each relaxed ordering
type will be activated according to its own capability bit.
This will align the DevX flow with the verbs implementation of
ibv_reg_mr when using the flag IBV_ACCESS_RELAXED_ORDERING
Fixes: 53ac93f71a ("net/mlx5: create relaxed ordering memory regions")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
129 lines
3.1 KiB
C
129 lines
3.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2019 Mellanox Technologies, Ltd
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*/
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#include <rte_malloc.h>
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#include <rte_errno.h>
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#include "mlx5_vdpa_utils.h"
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#include "mlx5_vdpa.h"
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int
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mlx5_vdpa_logging_enable(struct mlx5_vdpa_priv *priv, int enable)
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{
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struct mlx5_devx_virtq_attr attr = {
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.type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE,
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.dirty_bitmap_dump_enable = enable,
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};
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int i;
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for (i = 0; i < priv->nr_virtqs; ++i) {
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attr.queue_index = i;
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if (!priv->virtqs[i].virtq) {
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DRV_LOG(DEBUG, "virtq %d is invalid for dirty bitmap "
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"enabling.", i);
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} else if (mlx5_devx_cmd_modify_virtq(priv->virtqs[i].virtq,
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&attr)) {
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DRV_LOG(ERR, "Failed to modify virtq %d for dirty "
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"bitmap enabling.", i);
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return -1;
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}
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}
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return 0;
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}
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int
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mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base,
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uint64_t log_size)
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{
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struct mlx5_devx_mkey_attr mkey_attr = {
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.addr = (uintptr_t)log_base,
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.size = log_size,
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.pd = priv->pdn,
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.pg_access = 1,
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.klm_array = NULL,
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.klm_num = 0,
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.relaxed_ordering_read = 0,
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.relaxed_ordering_write = 0,
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};
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struct mlx5_devx_virtq_attr attr = {
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.type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS,
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.dirty_bitmap_addr = log_base,
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.dirty_bitmap_size = log_size,
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};
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struct mlx5_vdpa_query_mr *mr = rte_malloc(__func__, sizeof(*mr), 0);
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int i;
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if (!mr) {
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DRV_LOG(ERR, "Failed to allocate mem for lm mr.");
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return -1;
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}
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mr->umem = mlx5_glue->devx_umem_reg(priv->ctx,
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(void *)(uintptr_t)log_base,
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log_size, IBV_ACCESS_LOCAL_WRITE);
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if (!mr->umem) {
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DRV_LOG(ERR, "Failed to register umem for lm mr.");
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goto err;
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}
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mkey_attr.umem_id = mr->umem->umem_id;
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mr->mkey = mlx5_devx_cmd_mkey_create(priv->ctx, &mkey_attr);
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if (!mr->mkey) {
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DRV_LOG(ERR, "Failed to create Mkey for lm.");
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goto err;
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}
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attr.dirty_bitmap_mkey = mr->mkey->id;
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for (i = 0; i < priv->nr_virtqs; ++i) {
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attr.queue_index = i;
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if (!priv->virtqs[i].virtq) {
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DRV_LOG(DEBUG, "virtq %d is invalid for LM.", i);
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} else if (mlx5_devx_cmd_modify_virtq(priv->virtqs[i].virtq,
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&attr)) {
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DRV_LOG(ERR, "Failed to modify virtq %d for LM.", i);
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goto err;
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}
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}
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mr->is_indirect = 0;
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SLIST_INSERT_HEAD(&priv->mr_list, mr, next);
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return 0;
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err:
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if (mr->mkey)
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mlx5_devx_cmd_destroy(mr->mkey);
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if (mr->umem)
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mlx5_glue->devx_umem_dereg(mr->umem);
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rte_free(mr);
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return -1;
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}
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#define MLX5_VDPA_USED_RING_LEN(size) \
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((size) * sizeof(struct vring_used_elem) + sizeof(uint16_t) * 3)
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int
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mlx5_vdpa_lm_log(struct mlx5_vdpa_priv *priv)
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{
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uint64_t features;
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int ret = rte_vhost_get_negotiated_features(priv->vid, &features);
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int i;
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if (ret) {
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DRV_LOG(ERR, "Failed to get negotiated features.");
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return -1;
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}
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if (!RTE_VHOST_NEED_LOG(features))
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return 0;
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for (i = 0; i < priv->nr_virtqs; ++i) {
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if (!priv->virtqs[i].virtq) {
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DRV_LOG(DEBUG, "virtq %d is invalid for LM log.", i);
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} else {
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ret = mlx5_vdpa_virtq_stop(priv, i);
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if (ret) {
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DRV_LOG(ERR, "Failed to stop virtq %d for LM "
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"log.", i);
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return -1;
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}
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}
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rte_vhost_log_used_vring(priv->vid, i, 0,
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MLX5_VDPA_USED_RING_LEN(priv->virtqs[i].vq_size));
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}
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return 0;
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}
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