5c6942fdb9
Typically when the PMD issues a Rx command to DPAA2 hardware, the HW writes the available descriptors into the given memory. The RX function then processes the frames and prepare them as mbufs. This patch adds support to issue another pull request to hardware in another memory location, before we start processing the output of the first request. This help in controlling the CPU cycles wasted during the wait for the hardware to write the descriptors. Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
454 lines
14 KiB
C
454 lines
14 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright (c) 2016 NXP. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Freescale Semiconductor, Inc nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <time.h>
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#include <net/if.h>
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#include <rte_mbuf.h>
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#include <rte_ethdev.h>
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#include <rte_malloc.h>
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#include <rte_memcpy.h>
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#include <rte_string_fns.h>
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#include <rte_dev.h>
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#include <rte_ethdev.h>
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#include <fslmc_logs.h>
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#include <fslmc_vfio.h>
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#include <dpaa2_hw_pvt.h>
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#include <dpaa2_hw_dpio.h>
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#include <dpaa2_hw_mempool.h>
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#include "dpaa2_ethdev.h"
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#include "base/dpaa2_hw_dpni_annot.h"
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static inline uint32_t __attribute__((hot))
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dpaa2_dev_rx_parse(uint64_t hw_annot_addr)
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{
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uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
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struct dpaa2_annot_hdr *annotation =
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(struct dpaa2_annot_hdr *)hw_annot_addr;
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PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4);
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if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
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pkt_type = RTE_PTYPE_L2_ETHER_ARP;
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goto parse_done;
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} else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
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pkt_type = RTE_PTYPE_L2_ETHER;
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} else {
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goto parse_done;
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}
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if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
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L3_IPV4_N_PRESENT)) {
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pkt_type |= RTE_PTYPE_L3_IPV4;
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if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
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L3_IP_N_OPT_PRESENT))
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pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
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} else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
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L3_IPV6_N_PRESENT)) {
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pkt_type |= RTE_PTYPE_L3_IPV6;
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if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
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L3_IP_N_OPT_PRESENT))
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pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
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} else {
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goto parse_done;
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}
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if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
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L3_IP_1_MORE_FRAGMENT |
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L3_IP_N_FIRST_FRAGMENT |
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L3_IP_N_MORE_FRAGMENT)) {
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pkt_type |= RTE_PTYPE_L4_FRAG;
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goto parse_done;
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} else {
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pkt_type |= RTE_PTYPE_L4_NONFRAG;
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}
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if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
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pkt_type |= RTE_PTYPE_L4_UDP;
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else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
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pkt_type |= RTE_PTYPE_L4_TCP;
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else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
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pkt_type |= RTE_PTYPE_L4_SCTP;
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else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
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pkt_type |= RTE_PTYPE_L4_ICMP;
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else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
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pkt_type |= RTE_PTYPE_UNKNOWN;
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parse_done:
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return pkt_type;
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}
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static inline void __attribute__((hot))
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dpaa2_dev_rx_offload(uint64_t hw_annot_addr, struct rte_mbuf *mbuf)
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{
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struct dpaa2_annot_hdr *annotation =
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(struct dpaa2_annot_hdr *)hw_annot_addr;
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if (BIT_ISSET_AT_POS(annotation->word3,
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L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))
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mbuf->ol_flags |= PKT_RX_VLAN_PKT;
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if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
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mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
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if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
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mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
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}
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static inline struct rte_mbuf *__attribute__((hot))
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eth_fd_to_mbuf(const struct qbman_fd *fd)
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{
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struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(
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DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
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rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
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/* need to repopulated some of the fields,
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* as they may have changed in last transmission
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*/
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mbuf->nb_segs = 1;
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mbuf->ol_flags = 0;
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mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
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mbuf->data_len = DPAA2_GET_FD_LEN(fd);
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mbuf->pkt_len = mbuf->data_len;
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/* Parse the packet */
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/* parse results are after the private - sw annotation area */
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mbuf->packet_type = dpaa2_dev_rx_parse(
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(uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
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+ DPAA2_FD_PTA_SIZE);
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dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR(
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DPAA2_GET_FD_ADDR(fd)) +
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DPAA2_FD_PTA_SIZE, mbuf);
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mbuf->next = NULL;
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rte_mbuf_refcnt_set(mbuf, 1);
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PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
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"fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n",
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mbuf, mbuf->buf_addr, mbuf->data_off,
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DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
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rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
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DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
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return mbuf;
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}
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static void __rte_noinline __attribute__((hot))
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eth_mbuf_to_fd(struct rte_mbuf *mbuf,
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struct qbman_fd *fd, uint16_t bpid)
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{
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/*Resetting the buffer pool id and offset field*/
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fd->simple.bpid_offset = 0;
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DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));
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DPAA2_SET_FD_LEN(fd, mbuf->data_len);
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DPAA2_SET_FD_BPID(fd, bpid);
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DPAA2_SET_FD_OFFSET(fd, mbuf->data_off);
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DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
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PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d,"
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"fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n",
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mbuf, mbuf->buf_addr, mbuf->data_off,
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DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
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rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
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DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
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}
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static inline int __attribute__((hot))
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eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
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struct qbman_fd *fd, uint16_t bpid)
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{
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struct rte_mbuf *m;
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void *mb = NULL;
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if (rte_dpaa2_mbuf_alloc_bulk(
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rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) {
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PMD_TX_LOG(WARNING, "Unable to allocated DPAA2 buffer");
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rte_pktmbuf_free(mbuf);
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return -1;
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}
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m = (struct rte_mbuf *)mb;
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memcpy((char *)m->buf_addr + mbuf->data_off,
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(void *)((char *)mbuf->buf_addr + mbuf->data_off),
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mbuf->pkt_len);
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/* Copy required fields */
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m->data_off = mbuf->data_off;
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m->ol_flags = mbuf->ol_flags;
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m->packet_type = mbuf->packet_type;
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m->tx_offload = mbuf->tx_offload;
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/*Resetting the buffer pool id and offset field*/
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fd->simple.bpid_offset = 0;
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DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(m));
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DPAA2_SET_FD_LEN(fd, mbuf->data_len);
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DPAA2_SET_FD_BPID(fd, bpid);
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DPAA2_SET_FD_OFFSET(fd, mbuf->data_off);
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DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
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PMD_TX_LOG(DEBUG, " mbuf %p BMAN buf addr %p",
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(void *)mbuf, mbuf->buf_addr);
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PMD_TX_LOG(DEBUG, " fdaddr =%lx bpid =%d meta =%d off =%d, len =%d",
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DPAA2_GET_FD_ADDR(fd),
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DPAA2_GET_FD_BPID(fd),
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rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
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DPAA2_GET_FD_OFFSET(fd),
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DPAA2_GET_FD_LEN(fd));
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/*free the original packet */
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rte_pktmbuf_free(mbuf);
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return 0;
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}
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uint16_t
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dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
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{
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/* Function receive frames for a given device and VQ*/
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struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
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struct qbman_result *dq_storage;
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uint32_t fqid = dpaa2_q->fqid;
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int ret, num_rx = 0;
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uint8_t is_last = 0, status;
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struct qbman_swp *swp;
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const struct qbman_fd *fd[DPAA2_DQRR_RING_SIZE];
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struct qbman_pull_desc pulldesc;
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struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
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struct rte_eth_dev *dev = dpaa2_q->dev;
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if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
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ret = dpaa2_affine_qbman_swp();
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if (ret) {
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RTE_LOG(ERR, PMD, "Failure in affining portal\n");
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return 0;
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}
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}
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swp = DPAA2_PER_LCORE_PORTAL;
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if (!q_storage->active_dqs) {
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q_storage->toggle = 0;
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dq_storage = q_storage->dq_storage[q_storage->toggle];
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qbman_pull_desc_clear(&pulldesc);
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qbman_pull_desc_set_numframes(&pulldesc,
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(nb_pkts > DPAA2_DQRR_RING_SIZE) ?
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DPAA2_DQRR_RING_SIZE : nb_pkts);
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qbman_pull_desc_set_fq(&pulldesc, fqid);
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qbman_pull_desc_set_storage(&pulldesc, dq_storage,
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(dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
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if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
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while (!qbman_check_command_complete(swp,
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get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
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;
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clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
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}
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while (1) {
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if (qbman_swp_pull(swp, &pulldesc)) {
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PMD_RX_LOG(WARNING, "VDQ command is not issued."
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"QBMAN is busy\n");
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/* Portal was busy, try again */
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continue;
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}
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break;
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}
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q_storage->active_dqs = dq_storage;
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q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
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set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage);
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}
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dq_storage = q_storage->active_dqs;
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/* Check if the previous issued command is completed.
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* Also seems like the SWP is shared between the Ethernet Driver
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* and the SEC driver.
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*/
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while (!qbman_check_command_complete(swp, dq_storage))
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;
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if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
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clear_swp_active_dqs(q_storage->active_dpio_id);
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while (!is_last) {
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/* Loop until the dq_storage is updated with
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* new token by QBMAN
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*/
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while (!qbman_result_has_new_result(swp, dq_storage))
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;
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rte_prefetch0((void *)((uint64_t)(dq_storage + 1)));
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/* Check whether Last Pull command is Expired and
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* setting Condition for Loop termination
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*/
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if (qbman_result_DQ_is_pull_complete(dq_storage)) {
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is_last = 1;
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/* Check for valid frame. */
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status = (uint8_t)qbman_result_DQ_flags(dq_storage);
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if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
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continue;
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}
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fd[num_rx] = qbman_result_DQ_fd(dq_storage);
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/* Prefetch Annotation address for the parse results */
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rte_prefetch0((void *)((uint64_t)DPAA2_GET_FD_ADDR(fd[num_rx])
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+ DPAA2_FD_PTA_SIZE + 16));
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bufs[num_rx] = eth_fd_to_mbuf(fd[num_rx]);
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bufs[num_rx]->port = dev->data->port_id;
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if (dev->data->dev_conf.rxmode.hw_vlan_strip)
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rte_vlan_strip(bufs[num_rx]);
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dq_storage++;
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num_rx++;
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}
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if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
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while (!qbman_check_command_complete(swp,
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get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
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;
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clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
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}
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q_storage->toggle ^= 1;
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dq_storage = q_storage->dq_storage[q_storage->toggle];
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qbman_pull_desc_clear(&pulldesc);
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qbman_pull_desc_set_numframes(&pulldesc, DPAA2_DQRR_RING_SIZE);
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qbman_pull_desc_set_fq(&pulldesc, fqid);
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qbman_pull_desc_set_storage(&pulldesc, dq_storage,
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(dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
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/* Issue a volatile dequeue command. */
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while (1) {
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if (qbman_swp_pull(swp, &pulldesc)) {
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PMD_RX_LOG(WARNING, "VDQ command is not issued."
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"QBMAN is busy\n");
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continue;
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}
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break;
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}
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q_storage->active_dqs = dq_storage;
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q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
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set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage);
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dpaa2_q->rx_pkts += num_rx;
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/* Return the total number of packets received to DPAA2 app */
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return num_rx;
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}
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/*
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* Callback to handle sending packets through WRIOP based interface
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*/
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uint16_t
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dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
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{
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/* Function to transmit the frames to given device and VQ*/
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uint32_t loop;
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int32_t ret;
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struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
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uint32_t frames_to_send;
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struct rte_mempool *mp;
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struct qbman_eq_desc eqdesc;
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struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
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struct qbman_swp *swp;
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uint16_t num_tx = 0;
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uint16_t bpid;
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struct rte_eth_dev *dev = dpaa2_q->dev;
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struct dpaa2_dev_priv *priv = dev->data->dev_private;
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if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
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ret = dpaa2_affine_qbman_swp();
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if (ret) {
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RTE_LOG(ERR, PMD, "Failure in affining portal\n");
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return 0;
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}
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}
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swp = DPAA2_PER_LCORE_PORTAL;
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PMD_TX_LOG(DEBUG, "===> dev =%p, fqid =%d", dev, dpaa2_q->fqid);
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/*Prepare enqueue descriptor*/
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qbman_eq_desc_clear(&eqdesc);
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qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
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qbman_eq_desc_set_response(&eqdesc, 0, 0);
|
|
qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
|
|
dpaa2_q->flow_id, dpaa2_q->tc_index);
|
|
|
|
/*Clear the unused FD fields before sending*/
|
|
while (nb_pkts) {
|
|
frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;
|
|
|
|
for (loop = 0; loop < frames_to_send; loop++) {
|
|
fd_arr[loop].simple.frc = 0;
|
|
DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
|
|
DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
|
|
mp = (*bufs)->pool;
|
|
/* Not a hw_pkt pool allocated frame */
|
|
if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
|
|
PMD_TX_LOG(ERR, "non hw offload bufffer ");
|
|
/* alloc should be from the default buffer pool
|
|
* attached to this interface
|
|
*/
|
|
if (priv->bp_list) {
|
|
bpid = priv->bp_list->buf_pool.bpid;
|
|
} else {
|
|
PMD_TX_LOG(ERR, "errr: why no bpool"
|
|
" attached");
|
|
num_tx = 0;
|
|
goto skip_tx;
|
|
}
|
|
if (eth_copy_mbuf_to_fd(*bufs,
|
|
&fd_arr[loop], bpid)) {
|
|
bufs++;
|
|
continue;
|
|
}
|
|
} else {
|
|
bpid = mempool_to_bpid(mp);
|
|
eth_mbuf_to_fd(*bufs, &fd_arr[loop], bpid);
|
|
}
|
|
bufs++;
|
|
}
|
|
loop = 0;
|
|
while (loop < frames_to_send) {
|
|
loop += qbman_swp_send_multiple(swp, &eqdesc,
|
|
&fd_arr[loop], frames_to_send - loop);
|
|
}
|
|
|
|
num_tx += frames_to_send;
|
|
dpaa2_q->tx_pkts += frames_to_send;
|
|
nb_pkts -= frames_to_send;
|
|
}
|
|
skip_tx:
|
|
return num_tx;
|
|
}
|