295968d174
Add 'RTE_ETH' namespace to all enums & macros in a backward compatible way. The macros for backward compatibility can be removed in next LTS. Also updated some struct names to have 'rte_eth' prefix. All internal components switched to using new names. Syntax fixed on lines that this patch touches. Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com> Acked-by: Tyler Retzlaff <roretzla@linux.microsoft.com> Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Acked-by: Jerin Jacob <jerinj@marvell.com> Acked-by: Wisam Jaddo <wisamm@nvidia.com> Acked-by: Rosen Xu <rosen.xu@intel.com> Acked-by: Chenbo Xia <chenbo.xia@intel.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com> Acked-by: Somnath Kotur <somnath.kotur@broadcom.com>
195 lines
6.5 KiB
C
195 lines
6.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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* Copyright 2015 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX5_DEFS_H_
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#define RTE_PMD_MLX5_DEFS_H_
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#include <ethdev_driver.h>
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#include <rte_vxlan.h>
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#include <mlx5_common_defs.h>
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#include "mlx5_autoconf.h"
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/* Maximum number of simultaneous VLAN filters. */
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#define MLX5_MAX_VLAN_IDS 128
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/*
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* Request TX completion every time descriptors reach this threshold since
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* the previous request. Must be a power of two for performance reasons.
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*/
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#define MLX5_TX_COMP_THRESH 32u
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/*
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* Request TX completion every time the total number of WQEBBs used for inlining
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* packets exceeds the size of WQ divided by this divisor. Better to be power of
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* two for performance.
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*/
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#define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
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/*
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* Maximal amount of normal completion CQEs
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* processed in one call of tx_burst() routine.
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*/
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#define MLX5_TX_COMP_MAX_CQE 2u
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/*
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* If defined, only use software counters. The PMD will never ask the hardware
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* for these, and many of them won't be available.
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*/
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#ifndef MLX5_PMD_SOFT_COUNTERS
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#define MLX5_PMD_SOFT_COUNTERS 1
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#endif
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/* Alarm timeout. */
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#define MLX5_ALARM_TIMEOUT_US 100000
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/* Maximum number of extended statistics counters. */
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#define MLX5_MAX_XSTATS 32
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/* Maximum Packet headers size (L2+L3+L4) for TSO. */
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#define MLX5_MAX_TSO_HEADER (128u + 34u)
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/* Inline data size required by NICs. */
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#define MLX5_INLINE_HSIZE_NONE 0
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#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_vlan_hdr))
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#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \
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sizeof(struct rte_ipv6_hdr))
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#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \
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sizeof(struct rte_tcp_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \
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sizeof(struct rte_udp_hdr) + \
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sizeof(struct rte_vxlan_hdr) + \
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sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_vlan_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \
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sizeof(struct rte_ipv6_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \
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sizeof(struct rte_tcp_hdr))
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/* Threshold of buffer replenishment for vectorized Rx. */
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#define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
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(RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
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/* Maximum size of burst for vectorized Rx. */
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#define MLX5_VPMD_RX_MAX_BURST 64U
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/* Recommended optimal burst size. */
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#define MLX5_RX_DEFAULT_BURST 64U
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#define MLX5_TX_DEFAULT_BURST 64U
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/* Number of packets vectorized Rx can simultaneously process in a loop. */
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#define MLX5_VPMD_DESCS_PER_LOOP 4
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/* Mask of RSS on source only or destination only. */
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#define MLX5_RSS_SRC_DST_ONLY (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \
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RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
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/* Supported RSS */
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#define MLX5_RSS_HF_MASK (~(RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP | \
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MLX5_RSS_SRC_DST_ONLY))
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/* Timeout in seconds to get a valid link status. */
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#define MLX5_LINK_STATUS_TIMEOUT 10
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/* Number of times to retry retrieving the physical link information. */
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#define MLX5_GET_LINK_STATUS_RETRY_COUNT 3
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/* Maximum number of UAR pages used by a port,
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* These are the size and mask for an array of mutexes used to synchronize
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* the access to port's UARs on platforms that do not support 64 bit writes.
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* In such systems it is possible to issue the 64 bits DoorBells through two
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* consecutive writes, each write 32 bits. The access to a UAR page (which can
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* be accessible by all threads in the process) must be synchronized
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* (for example, using a semaphore). Such a synchronization is not required
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* when ringing DoorBells on different UAR pages.
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* A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared
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* among the ports.
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*/
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#define MLX5_UAR_PAGE_NUM_MAX 64
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#define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)
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/* Fields of memory mapping type in offset parameter of mmap() */
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#define MLX5_UAR_MMAP_CMD_SHIFT 8
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#define MLX5_UAR_MMAP_CMD_MASK 0xff
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#ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD
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#define MLX5_MMAP_GET_NC_PAGES_CMD 3
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#endif
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/* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */
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#define MLX5_MPRQ_STRIDE_NUM_N 6U
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/* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */
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#define MLX5_MPRQ_STRIDE_SIZE_N 11U
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/* Two-byte shift is disabled for Multi-Packet RQ. */
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#define MLX5_MPRQ_TWO_BYTE_SHIFT 0
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/*
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* Minimum size of packet to be memcpy'd instead of being attached as an
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* external buffer.
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*/
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#define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128
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/* Minimum number Rx queues to enable Multi-Packet RQ. */
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#define MLX5_MPRQ_MIN_RXQS 12
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/* Cache size of mempool for Multi-Packet RQ. */
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#define MLX5_MPRQ_MP_CACHE_SZ 32U
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/* MLX5_DV_XMETA_EN supported values. */
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#define MLX5_XMETA_MODE_LEGACY 0
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#define MLX5_XMETA_MODE_META16 1
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#define MLX5_XMETA_MODE_META32 2
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/* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */
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#define MLX5_XMETA_MODE_MISS_INFO 3
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/* Tx accurate scheduling on timestamps parameters. */
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#define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */
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#define MLX5_TXPP_CLKQ_SIZE 1
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#define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4)
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#define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \
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MLX5_TXPP_REARM) * 2)
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#define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2)
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/* The minimal size test packet to put into one WQE, padded by HW. */
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#define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_ipv4_hdr))
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/* Size of the simple hash table for metadata register table. */
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#define MLX5_FLOW_MREG_HTABLE_SZ 64
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#define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE"
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#define MLX5_DEFAULT_COPY_ID UINT32_MAX
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/* Size of the simple hash table for header modify table. */
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#define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 15)
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/* Size of the simple hash table for encap decap table. */
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#define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 12)
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/* Size of the hash table for tag table. */
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#define MLX5_TAGS_HLIST_ARRAY_SIZE (1 << 15)
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/* Size fo the hash table for SFT table. */
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#define MLX5_FLOW_SFT_HLIST_ARRAY_SIZE 4096
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/* Hairpin TX/RX queue configuration parameters. */
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#define MLX5_HAIRPIN_QUEUE_STRIDE 6
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#define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2)
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/* Maximum number of indirect actions supported by rte_flow */
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#define MLX5_MAX_INDIRECT_ACTIONS 3
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/*
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* Linux definition of static_assert is found in /usr/include/assert.h.
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* Windows does not require a redefinition.
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*/
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#if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS)
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#define static_assert _Static_assert
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#endif
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#endif /* RTE_PMD_MLX5_DEFS_H_ */
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