1029 lines
32 KiB
C
1029 lines
32 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2012-2018 Solarflare Communications Inc.
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* All rights reserved.
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*/
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/*
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* This is NOT the original source file. Do NOT edit it.
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* To update the tlv layout, please edit the copy in
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* the sfregistry repo and then, in that repo,
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* "make tlv_headers" or "make export" to
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* regenerate and export all types of headers.
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*/
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/* These structures define the layouts for the TLV items stored in static and
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* dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
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*
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* They contain the same sort of information that was kept in the
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* siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
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* (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
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* Siena.
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*
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* These are used directly by the MC and should also be usable directly on host
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* systems which are little-endian and do not do strange things with structure
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* padding. (Big-endian host systems will require some byte-swapping.)
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*
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* -----
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*
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* Please refer to SF-108797-SW for a general overview of the TLV partition
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* format.
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*
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* -----
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*
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* The current tag IDs have a general structure: with the exception of the
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* special values defined in the document, they are of the form 0xLTTTNNNN,
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* where:
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*
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* - L is a location, indicating where this tag is expected to be found:
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* 0: static configuration
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* 1: dynamic configuration
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* 2: firmware internal use
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* 3: license partition
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* 4: tsa configuration
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*
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* - TTT is a type, which is just a unique value. The same type value
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* might appear in both locations, indicating a relationship between
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* the items (e.g. static and dynamic VPD below).
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*
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* - NNNN is an index of some form. Some item types are per-port, some
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* are per-PF, some are per-partition-type.
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*
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* -----
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*
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* As with the previous Siena structures, each structure here is laid out
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* carefully: values are aligned to their natural boundary, with explicit
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* padding fields added where necessary. (No, technically this does not
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* absolutely guarantee portability. But, in practice, compilers are generally
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* sensible enough not to introduce completely pointless padding, and it works
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* well enough.)
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*/
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#ifndef CI_MGMT_TLV_LAYOUT_H
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#define CI_MGMT_TLV_LAYOUT_H
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/* ----------------------------------------------------------------------------
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* General structure (defined by SF-108797-SW)
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* ----------------------------------------------------------------------------
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*/
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/* The "end" tag.
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*
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* (Note that this is *not* followed by length or value fields: anything after
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* the tag itself is irrelevant.)
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*/
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#define TLV_TAG_END (0xEEEEEEEE)
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/* Other special reserved tag values.
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*/
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#define TLV_TAG_SKIP (0x00000000)
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#define TLV_TAG_INVALID (0xFFFFFFFF)
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/* TLV partition header.
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*
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* In a TLV partition, this must be the first item in the sequence, at offset
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* 0.
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*/
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#define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
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struct tlv_partition_header {
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uint32_t tag;
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uint32_t length;
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uint16_t type_id;
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/* 0 indicates the default segment (always located at offset 0), while other values
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* are for RFID-selectable presets that should immediately follow the default segment.
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* The default segment may also have preset > 0, which means that it is a preset
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* selected through an RFID command and copied by FW to the location at offset 0. */
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uint16_t preset;
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uint32_t generation;
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uint32_t total_length;
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};
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/* TLV partition trailer.
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*
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* In a TLV partition, this must be the last item in the sequence, immediately
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* preceding the TLV_TAG_END word.
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*/
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#define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
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struct tlv_partition_trailer {
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uint32_t tag;
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uint32_t length;
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uint32_t generation;
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uint32_t checksum;
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};
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/* Appendable TLV partition header.
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*
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* In an appendable TLV partition, this must be the first item in the sequence,
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* at offset 0. (Note that, unlike the configuration partitions, there is no
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* trailer before the TLV_TAG_END word.)
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*/
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#define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
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struct tlv_appendable_partition_header {
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uint32_t tag;
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uint32_t length;
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uint16_t type_id;
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uint16_t reserved;
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};
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/* ----------------------------------------------------------------------------
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* Configuration items
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* ----------------------------------------------------------------------------
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*/
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/* NIC global capabilities.
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*/
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#define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
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struct tlv_global_capabilities {
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uint32_t tag;
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uint32_t length;
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uint32_t flags;
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};
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/* Siena-style per-port MAC address allocation.
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*
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* There are <count> addresses, starting at <base_address> and incrementing
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* by adding <stride> to the low-order byte(s).
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*
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* (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
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* of contiguous MAC addresses for the firmware to allocate as it sees fit.)
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*/
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#define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
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struct tlv_port_mac {
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uint32_t tag;
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uint32_t length;
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uint8_t base_address[6];
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uint16_t reserved;
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uint16_t count;
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uint16_t stride;
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};
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/* Static VPD.
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*
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* This is the portion of VPD which is set at manufacturing time and not
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* expected to change. It is formatted as a standard PCI VPD block. There are
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* global and per-pf TLVs for this, the global TLV is new for Medford and is
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* used in preference to the per-pf TLV.
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*/
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#define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
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struct tlv_pf_static_vpd {
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uint32_t tag;
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uint32_t length;
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uint8_t bytes[];
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};
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#define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
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struct tlv_global_static_vpd {
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uint32_t tag;
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uint32_t length;
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uint8_t bytes[];
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};
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/* Dynamic VPD.
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*
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* This is the portion of VPD which may be changed (e.g. by firmware updates).
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* It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
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* for this, the global TLV is new for Medford and is used in preference to the
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* per-pf TLV.
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*/
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#define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
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struct tlv_pf_dynamic_vpd {
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uint32_t tag;
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uint32_t length;
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uint8_t bytes[];
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};
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#define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
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struct tlv_global_dynamic_vpd {
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uint32_t tag;
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uint32_t length;
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uint8_t bytes[];
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};
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/* "DBI" PCI config space changes.
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*
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* This is a set of edits made to the default PCI config space values before
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* the device is allowed to enumerate. There are global and per-pf TLVs for
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* this, the global TLV is new for Medford and is used in preference to the
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* per-pf TLV.
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*/
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#define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
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struct tlv_pf_dbi {
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uint32_t tag;
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uint32_t length;
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struct {
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uint16_t addr;
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uint16_t byte_enables;
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uint32_t value;
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} items[];
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};
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#define TLV_TAG_GLOBAL_DBI (0x00210000)
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struct tlv_global_dbi {
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uint32_t tag;
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uint32_t length;
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struct {
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uint16_t addr;
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uint16_t byte_enables;
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uint32_t value;
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} items[];
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};
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/* Partition subtype codes.
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*
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* A subtype may optionally be stored for each type of partition present in
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* the NVRAM. For example, this may be used to allow a generic firmware update
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* utility to select a specific variant of firmware for a specific variant of
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* board.
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*
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* The description[] field is an optional string which is returned in the
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* MC_CMD_NVRAM_METADATA response if present.
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*/
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#define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
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struct tlv_partition_subtype {
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uint32_t tag;
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uint32_t length;
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uint32_t subtype;
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uint8_t description[];
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};
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/* Partition version codes.
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*
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* A version may optionally be stored for each type of partition present in
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* the NVRAM. This provides a standard way of tracking the currently stored
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* version of each of the various component images.
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*/
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#define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
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struct tlv_partition_version {
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uint32_t tag;
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uint32_t length;
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uint16_t version_w;
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uint16_t version_x;
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uint16_t version_y;
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uint16_t version_z;
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};
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/* Global PCIe configuration */
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#define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
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struct tlv_pcie_config {
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uint32_t tag;
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uint32_t length;
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int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
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uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
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uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
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uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
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#define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
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#define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
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};
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/* Per-PF configuration. Note that not all these fields are necessarily useful
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* as the apertures are constrained by the BIU settings (the one case we do
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* use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
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* tidy things up later */
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#define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
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struct tlv_per_pf_pcie_config {
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uint32_t tag;
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uint32_t length;
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uint8_t vfs_total;
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uint8_t port_allocation;
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uint16_t vectors_per_pf;
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uint16_t vectors_per_vf;
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uint8_t pf_bar0_aperture;
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uint8_t pf_bar2_aperture;
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uint8_t vf_bar0_aperture;
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uint8_t vf_base;
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uint16_t supp_pagesz;
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uint16_t msix_vec_base;
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};
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/* Development ONLY. This is a single TLV tag for all the gubbins
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* that can be set through the MC command-line other than the PCIe
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* settings. This is a temporary measure. */
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#define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
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#define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
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struct tlv_tmp_gubbins {
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uint32_t tag;
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uint32_t length;
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/* Consumed by dpcpu.c */
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uint64_t tx0_tags; /* Bitmap */
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uint64_t tx1_tags; /* Bitmap */
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uint64_t dl_tags; /* Bitmap */
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uint32_t flags;
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#define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
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#define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
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#define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
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#define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
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#define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
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/* Consumed by features.c */
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uint32_t dut_features; /* All 1s -> leave alone */
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int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
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/* Consumed by clocks_hunt.c */
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int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
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/* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
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int8_t rx_dc_size; /* -1 -> leave alone */
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int8_t tx_dc_size;
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int16_t num_q_allocs;
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};
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/* Global port configuration
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*
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* This is now deprecated in favour of a platform-provided default
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* and dynamic config override via tlv_global_port_options.
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*/
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#define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
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struct tlv_global_port_config {
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uint32_t tag;
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uint32_t length;
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uint32_t ports_per_core;
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uint32_t max_port_speed;
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};
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/* Firmware options.
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*
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* This is intended for user-configurable selection of optional firmware
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* features and variants.
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*
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* Initially, this consists only of the satellite CPU firmware variant
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* selection, but this tag could be extended in the future (using the
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* tag length to determine whether additional fields are present).
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*/
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#define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
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struct tlv_firmware_options {
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uint32_t tag;
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uint32_t length;
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uint32_t firmware_variant;
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#define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
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/* These are the values for overriding the driver's choice; the definitions
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* are taken from MCDI so that they don't get out of step. Include
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* <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
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* you need to use these constants.
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*/
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#define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
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#define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
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#define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
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#define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
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#define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
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MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
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#define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
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#define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK
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#define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP
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};
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/* Voltage settings
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*
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* Intended for boards with A0 silicon where the core voltage may
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* need tweaking. Most likely set once when the pass voltage is
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* determined. */
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#define TLV_TAG_0V9_SETTINGS (0x000c0000)
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struct tlv_0v9_settings {
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uint32_t tag;
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uint32_t length;
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uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
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#define TLV_TAG_0V9_REQUIRES_FAN (1)
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uint16_t target_voltage; /* In millivolts */
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/* Since the limits are meant to be centred to the target (and must at least
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* contain it) they need setting as well. */
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uint16_t warn_low; /* In millivolts */
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uint16_t warn_high; /* In millivolts */
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uint16_t panic_low; /* In millivolts */
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uint16_t panic_high; /* In millivolts */
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};
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/* Clock configuration */
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#define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
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#define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
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struct tlv_clock_config {
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uint32_t tag;
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uint32_t length;
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uint16_t clk_sys; /* MHz */
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uint16_t clk_dpcpu; /* MHz */
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uint16_t clk_icore; /* MHz */
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uint16_t clk_pcs; /* MHz */
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};
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#define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
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struct tlv_clock_config_medford {
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uint32_t tag;
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uint32_t length;
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uint16_t clk_sys; /* MHz */
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uint16_t clk_mc; /* MHz */
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uint16_t clk_rmon; /* MHz */
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uint16_t clk_vswitch; /* MHz */
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uint16_t clk_dpcpu; /* MHz */
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uint16_t clk_pcs; /* MHz */
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};
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/* EF10-style global pool of MAC addresses.
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*
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* There are <count> addresses, starting at <base_address>, which are
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* contiguous. Firmware is responsible for allocating addresses from this
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* pool to ports / PFs as appropriate.
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*/
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#define TLV_TAG_GLOBAL_MAC (0x000e0000)
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struct tlv_global_mac {
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uint32_t tag;
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uint32_t length;
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uint8_t base_address[6];
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uint16_t reserved1;
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uint16_t count;
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uint16_t reserved2;
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};
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#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
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#define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
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/* The target value for the 0v9 power rail measured on-chip at the
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* analogue test bus */
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struct tlv_0v9_atb_target {
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uint32_t tag;
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uint32_t length;
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uint16_t millivolts;
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uint16_t reserved;
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};
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/* Factory settings for amplitude calibration of the PCIE TX serdes */
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#define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
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struct tlv_pcie_tx_amp_config {
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uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t quad_tx_imp2k[4];
|
|
uint8_t quad_tx_imp50[4];
|
|
uint8_t lane_amp[16];
|
|
};
|
|
|
|
|
|
/* Global PCIe configuration, second revision. This represents the visible PFs
|
|
* by a bitmap rather than having the number of the highest visible one. As such
|
|
* it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
|
|
* can and it should be used in place of that tag in future (but compatibility with
|
|
* the old tag will be left in the firmware indefinitely). */
|
|
|
|
#define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
|
|
|
|
struct tlv_pcie_config_r2 {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint16_t visible_pfs; /**< Bitmap of visible PFs */
|
|
uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
|
|
uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
|
|
uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
|
|
};
|
|
|
|
/* Dynamic port mode.
|
|
*
|
|
* Allows selecting alternate port configuration for platforms that support it
|
|
* (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
|
|
* number of externally visible ports (and, hence, PF to port mapping), so must
|
|
* be done at boot time.
|
|
*
|
|
* Port mode naming convention is
|
|
*
|
|
* [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
|
|
*
|
|
* Port lane width determines the capabilities (speeds) of the ports, subject
|
|
* to architecture capabilities (e.g. 25G support) and switch bandwidth
|
|
* constraints:
|
|
* - single lane ports can do 25G/10G/1G
|
|
* - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
|
|
* - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
|
|
|
|
* This tag supercedes tlv_global_port_config.
|
|
*/
|
|
|
|
#define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
|
|
|
|
struct tlv_global_port_mode {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t port_mode;
|
|
#define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
|
|
|
|
/* Huntington port modes */
|
|
#define TLV_PORT_MODE_10G (0)
|
|
#define TLV_PORT_MODE_40G (1)
|
|
#define TLV_PORT_MODE_10G_10G (2)
|
|
#define TLV_PORT_MODE_40G_40G (3)
|
|
#define TLV_PORT_MODE_10G_10G_10G_10G (4)
|
|
#define TLV_PORT_MODE_40G_10G_10G (6)
|
|
#define TLV_PORT_MODE_10G_10G_40G (7)
|
|
|
|
/* Medford (and later) port modes */
|
|
#define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
|
|
#define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
|
|
#define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
|
|
#define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
|
|
#define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
|
|
#define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
|
|
#define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
|
|
#define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */
|
|
#define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
|
|
#define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
|
|
#define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
|
|
#define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
|
|
#define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
|
|
#define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
|
|
#define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
|
|
#define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
|
|
#define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
|
|
#define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
|
|
#define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
|
|
|
|
/* Snapper-only Medford2 port modes.
|
|
* These modes are eftest only, to allow snapper explicit
|
|
* selection between multi-channel and LLPCS. In production,
|
|
* this selection is automatic and outside world should not
|
|
* care about LLPCS.
|
|
*/
|
|
#define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
|
|
#define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
|
|
#define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
|
|
#define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
|
|
#define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
|
|
#define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
|
|
#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
|
|
|
|
/* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
|
|
#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
|
|
#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)
|
|
#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
|
|
#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
|
|
|
|
#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
|
|
};
|
|
|
|
/* Type of the v-switch created implicitly by the firmware */
|
|
|
|
#define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
|
|
|
|
struct tlv_vswitch_type {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t vswitch_type;
|
|
#define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
|
|
#define TLV_VSWITCH_TYPE_NONE (0)
|
|
#define TLV_VSWITCH_TYPE_VLAN (1)
|
|
#define TLV_VSWITCH_TYPE_VEB (2)
|
|
#define TLV_VSWITCH_TYPE_VEPA (3)
|
|
#define TLV_VSWITCH_TYPE_MUX (4)
|
|
#define TLV_VSWITCH_TYPE_TEST (5)
|
|
};
|
|
|
|
/* A VLAN tag for the v-port created implicitly by the firmware */
|
|
|
|
#define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
|
|
|
|
struct tlv_vport_vlan_tag {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t vlan_tag;
|
|
#define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
|
|
};
|
|
|
|
/* Offset to be applied to the 0v9 setting, wherever it came from */
|
|
|
|
#define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
|
|
|
|
struct tlv_0v9_atb_offset {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
int16_t offset_millivolts;
|
|
uint16_t reserved;
|
|
};
|
|
|
|
/* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
|
|
* The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
|
|
* TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
|
|
* TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
|
|
* Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
|
|
|
|
#define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
|
|
|
|
struct tlv_privilege_mask { /* legacy structure - do not use */
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t privilege_mask;
|
|
};
|
|
|
|
#define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
|
|
|
|
struct tlv_privilege_mask_add {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t privilege_mask_add;
|
|
};
|
|
|
|
#define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
|
|
|
|
struct tlv_privilege_mask_rem {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t privilege_mask_rem;
|
|
};
|
|
|
|
/* Additional privileges given to all PFs.
|
|
* This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
|
|
|
|
#define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
|
|
|
|
struct tlv_privilege_mask_add_all_pfs {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t privilege_mask_add;
|
|
};
|
|
|
|
/* Additional privileges given to a selected PF.
|
|
* This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
|
|
|
|
#define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
|
|
|
|
struct tlv_privilege_mask_add_single_pf {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t privilege_mask_add;
|
|
};
|
|
|
|
/* Turning on/off the PFIOV mode.
|
|
* This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
|
|
|
|
#define TLV_TAG_PFIOV(port) (0x10170000 + (port))
|
|
|
|
struct tlv_pfiov {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t pfiov;
|
|
#define TLV_PFIOV_OFF (0) /* Default */
|
|
#define TLV_PFIOV_ON (1)
|
|
};
|
|
|
|
/* Multicast filter chaining mode selection.
|
|
*
|
|
* When enabled, multicast packets are delivered to all recipients of all
|
|
* matching multicast filters, with the exception that IP multicast filters
|
|
* will steal traffic from MAC multicast filters on a per-function basis.
|
|
* (New behaviour.)
|
|
*
|
|
* When disabled, multicast packets will always be delivered only to the
|
|
* recipients of the highest priority matching multicast filter.
|
|
* (Legacy behaviour.)
|
|
*
|
|
* The DEFAULT mode (which is the same as the tag not being present at all)
|
|
* is equivalent to ENABLED in production builds, and DISABLED in eftest
|
|
* builds.
|
|
*
|
|
* This option is intended to provide run-time control over this feature
|
|
* while it is being stabilised and may be withdrawn at some point in the
|
|
* future; the new behaviour is intended to become the standard behaviour.
|
|
*/
|
|
|
|
#define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
|
|
|
|
struct tlv_mcast_filter_chaining {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t mode;
|
|
#define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
|
|
#define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
|
|
#define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
|
|
};
|
|
|
|
/* Pacer rate limit per PF */
|
|
#define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
|
|
|
|
struct tlv_rate_limit {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t rate_mbps;
|
|
};
|
|
|
|
/* OCSD Enable/Disable
|
|
*
|
|
* This setting allows OCSD to be disabled. This is a requirement for HP
|
|
* servers to support PCI passthrough for virtualization.
|
|
*
|
|
* The DEFAULT mode (which is the same as the tag not being present) is
|
|
* equivalent to ENABLED.
|
|
*
|
|
* This option is not used by the MCFW, and is entirely handled by the various
|
|
* drivers that support OCSD, by reading the setting before they attempt
|
|
* to enable OCSD.
|
|
*
|
|
* bit0: OCSD Disabled/Enabled
|
|
*/
|
|
|
|
#define TLV_TAG_OCSD (0x101C0000)
|
|
|
|
struct tlv_ocsd {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t mode;
|
|
#define TLV_OCSD_DISABLED 0
|
|
#define TLV_OCSD_ENABLED 1 /* Default */
|
|
};
|
|
|
|
/* Descriptor cache config.
|
|
*
|
|
* Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
|
|
* sets the total number of VIs. When the number of VIs is reduced VIs are taken
|
|
* away from the highest numbered port first, so a vi_count of 1024 means 1024
|
|
* VIs on the first port and 0 on the second (on a Torino).
|
|
*/
|
|
|
|
#define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
|
|
|
|
struct tlv_descriptor_cache_config {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t rx_desc_cache_size;
|
|
uint8_t tx_desc_cache_size;
|
|
uint16_t vi_count;
|
|
};
|
|
#define TLV_DESC_CACHE_DEFAULT (0xff)
|
|
#define TLV_VI_COUNT_DEFAULT (0xffff)
|
|
|
|
/* RX event merging config (read batching).
|
|
*
|
|
* Sets the global maximum number of events for the merging bins, and the
|
|
* global timeout configuration for the bins.
|
|
*/
|
|
|
|
#define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
|
|
|
|
struct tlv_rx_event_merging_config {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t max_events;
|
|
#define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
|
|
uint32_t timeout_ns;
|
|
};
|
|
#define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
|
|
#define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
|
|
|
|
#define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
|
|
struct tlv_pcie_link_settings {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
|
|
uint16_t width; /* Number of lanes */
|
|
};
|
|
|
|
/* TX event merging config.
|
|
*
|
|
* Sets the global maximum number of events for the merging bins, and the
|
|
* global timeout configuration for the bins, and the global timeout for
|
|
* empty queues.
|
|
*/
|
|
#define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
|
|
struct tlv_tx_event_merging_config {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t max_events;
|
|
#define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
|
|
uint32_t timeout_ns;
|
|
uint32_t qempty_timeout_ns; /* Medford only */
|
|
};
|
|
#define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
|
|
#define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
|
|
#define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
|
|
|
|
#define TLV_TAG_LICENSE (0x30800000)
|
|
|
|
typedef struct tlv_license {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t data[];
|
|
} tlv_license_t;
|
|
|
|
/* TSA NIC IP address configuration (DEPRECATED)
|
|
*
|
|
* Sets the TSA NIC IP address statically via configuration tool or dynamically
|
|
* via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
|
|
*
|
|
* NOTE: This TAG is temporarily placed in the dynamic config partition and will
|
|
* be moved to a private partition during TSA development. It is not used in any
|
|
* released code yet.
|
|
*/
|
|
|
|
#define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */
|
|
|
|
#define TLV_TSAN_IP_MODE_STATIC (0)
|
|
#define TLV_TSAN_IP_MODE_DHCP (1)
|
|
#define TLV_TSAN_IP_MODE_SNOOP (2)
|
|
typedef struct tlv_tsan_config {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t mode;
|
|
uint32_t ip;
|
|
uint32_t netmask;
|
|
uint32_t gateway;
|
|
uint32_t port;
|
|
uint32_t bind_retry; /* DEPRECATED */
|
|
uint32_t bind_bkout; /* DEPRECATED */
|
|
} tlv_tsan_config_t;
|
|
|
|
/* TSA Controller IP address configuration (DEPRECATED)
|
|
*
|
|
* Sets the TSA Controller IP address statically via configuration tool
|
|
*
|
|
* NOTE: This TAG is temporarily placed in the dynamic config partition and will
|
|
* be moved to a private partition during TSA development. It is not used in any
|
|
* released code yet.
|
|
*/
|
|
|
|
#define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */
|
|
|
|
#define TLV_MAX_TSACS (4)
|
|
typedef struct tlv_tsac_config {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint32_t num_tsacs;
|
|
uint32_t ip[TLV_MAX_TSACS];
|
|
uint32_t port[TLV_MAX_TSACS];
|
|
} tlv_tsac_config_t;
|
|
|
|
/* Binding ticket (DEPRECATED)
|
|
*
|
|
* Sets the TSA NIC binding ticket used for binding process between the TSA NIC
|
|
* and the TSA Controller
|
|
*
|
|
* NOTE: This TAG is temporarily placed in the dynamic config partition and will
|
|
* be moved to a private partition during TSA development. It is not used in any
|
|
* released code yet.
|
|
*/
|
|
|
|
#define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */
|
|
|
|
typedef struct tlv_binding_ticket {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t bytes[];
|
|
} tlv_binding_ticket_t;
|
|
|
|
/* Solarflare private key (DEPRECATED)
|
|
*
|
|
* Sets the Solareflare private key used for signing during the binding process
|
|
*
|
|
* NOTE: This TAG is temporarily placed in the dynamic config partition and will
|
|
* be moved to a private partition during TSA development. It is not used in any
|
|
* released code yet.
|
|
*/
|
|
|
|
#define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
|
|
|
|
typedef struct tlv_pik_sf {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t bytes[];
|
|
} tlv_pik_sf_t;
|
|
|
|
/* CA root certificate (DEPRECATED)
|
|
*
|
|
* Sets the CA root certificate used for TSA Controller verfication during
|
|
* TLS connection setup between the TSA NIC and the TSA Controller
|
|
*
|
|
* NOTE: This TAG is temporarily placed in the dynamic config partition and will
|
|
* be moved to a private partition during TSA development. It is not used in any
|
|
* released code yet.
|
|
*/
|
|
|
|
#define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */
|
|
|
|
typedef struct tlv_ca_root_cert {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t bytes[];
|
|
} tlv_ca_root_cert_t;
|
|
|
|
/* Tx vFIFO Low latency configuration
|
|
*
|
|
* To keep the desired booting behaviour for the switch, it just requires to
|
|
* know if the low latency mode is enabled.
|
|
*/
|
|
|
|
#define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
|
|
struct tlv_tx_vfifo_ull_mode {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t mode;
|
|
#define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
|
|
};
|
|
|
|
/* BIU mode
|
|
*
|
|
* Medford2 tag for selecting VI window decode (see values below)
|
|
*/
|
|
#define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
|
|
struct tlv_biu_vi_window_mode {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t mode;
|
|
#define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
|
|
#define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
|
|
#define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
|
|
};
|
|
|
|
/* FastPD mode
|
|
*
|
|
* Medford2 tag for configuring the FastPD mode (see values below)
|
|
*/
|
|
#define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
|
|
struct tlv_fastpd_mode {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t mode;
|
|
#define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
|
|
#define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
|
|
#define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
|
|
};
|
|
|
|
/* L3xUDP datapath firmware UDP port configuration
|
|
*
|
|
* Sets the list of UDP ports on which the encapsulation will be handled.
|
|
* The number of ports in the list is implied by the length of the TLV item.
|
|
*/
|
|
#define TLV_TAG_L3XUDP_PORTS (0x102a0000)
|
|
struct tlv_l3xudp_ports {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint16_t ports[];
|
|
#define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16
|
|
};
|
|
|
|
/* Wake on LAN setting
|
|
*
|
|
* Enables the Wake On Lan (WoL) functionality on the given port. This will be
|
|
* a persistent setting for manageability firmware. Drivers have direct access
|
|
* to WoL using MCDI.
|
|
*/
|
|
#define TLV_TAG_WAKE_ON_LAN(port) (0x102b0000 + (port))
|
|
struct tlv_wake_on_lan {
|
|
uint32_t tag;
|
|
uint32_t length;
|
|
uint8_t mode;
|
|
uint8_t bytes[];
|
|
#define TLV_WAKE_ON_LAN_MODE_DISABLED 0
|
|
#define TLV_WAKE_ON_LAN_MODE_MAGIC_PACKET 1
|
|
#define TLV_WAKE_ON_LAN_MAX_NUM_BYTES 255
|
|
};
|
|
|
|
#endif /* CI_MGMT_TLV_LAYOUT_H */
|