fa8f86a14e
Add meson build infrastructure along with HW definition header file. This patch also adds cross-compile configs for arm for CN9K series and CN10K series of Marvell SoC's. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Sunil Kumar Kori <skori@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Signed-off-by: Satha Rao <skoteshwar@marvell.com> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
33 lines
745 B
C
33 lines
745 B
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _ROC_BITS_H_
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#define _ROC_BITS_H_
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#ifndef BIT_ULL
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#define BIT_ULL(nr) (1ULL << (nr))
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#endif
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#ifndef BIT
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#define BIT(nr) (1UL << (nr))
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#endif
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#ifndef BITS_PER_LONG
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#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
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#endif
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#ifndef BITS_PER_LONG_LONG
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#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
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#endif
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#ifndef GENMASK
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#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
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#endif
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#ifndef GENMASK_ULL
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#define GENMASK_ULL(h, l) \
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(((~0ULL) - (1ULL << (l)) + 1) & \
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(~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
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#endif
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#endif /* _ROC_BITS_H_ */
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