309b553c26
Add TIM LF IRQ register and un-register functions. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#include "roc_api.h"
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#include "roc_priv.h"
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static void
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tim_lf_irq(void *param)
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{
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uintptr_t base = (uintptr_t)param;
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uint64_t intr;
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uint8_t ring;
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ring = (base >> 12) & 0xFF;
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intr = plt_read64(base + TIM_LF_NRSPERR_INT);
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plt_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr);
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intr = plt_read64(base + TIM_LF_RAS_INT);
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plt_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr);
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/* Clear interrupt */
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plt_write64(intr, base + TIM_LF_NRSPERR_INT);
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plt_write64(intr, base + TIM_LF_RAS_INT);
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}
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static int
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tim_lf_register_irq(uintptr_t base, struct plt_intr_handle *handle,
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uint16_t msix_offset)
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{
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unsigned int vec;
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int rc;
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vec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;
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/* Clear err interrupt */
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plt_write64(~0ull, base + TIM_LF_NRSPERR_INT);
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/* Set used interrupt vectors */
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rc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);
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/* Enable hw interrupt */
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plt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);
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vec = msix_offset + TIM_LF_INT_VEC_RAS_INT;
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/* Clear err interrupt */
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plt_write64(~0ull, base + TIM_LF_RAS_INT);
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/* Set used interrupt vectors */
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rc = dev_irq_register(handle, tim_lf_irq, (void *)base, vec);
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/* Enable hw interrupt */
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plt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);
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return rc;
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}
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int
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tim_register_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,
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uint8_t ring_id, uint16_t msix_offset)
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{
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struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
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uintptr_t base;
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if (msix_offset == MSIX_VECTOR_INVALID) {
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plt_err("Invalid MSIX offset for TIM LF %d", ring_id);
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return TIM_ERR_PARAM;
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}
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base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
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return tim_lf_register_irq(base, handle, msix_offset);
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}
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static void
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tim_lf_unregister_irq(uintptr_t base, struct plt_intr_handle *handle,
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uint16_t msix_offset)
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{
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unsigned int vec;
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vec = msix_offset + TIM_LF_INT_VEC_NRSPERR_INT;
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/* Clear err interrupt */
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plt_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);
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dev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);
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vec = msix_offset + TIM_LF_INT_VEC_RAS_INT;
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/* Clear err interrupt */
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plt_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);
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dev_irq_unregister(handle, tim_lf_irq, (void *)base, vec);
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}
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void
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tim_unregister_irq_priv(struct roc_tim *roc_tim, struct plt_intr_handle *handle,
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uint8_t ring_id, uint16_t msix_offset)
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{
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struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
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uintptr_t base;
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if (msix_offset == MSIX_VECTOR_INVALID) {
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plt_err("Invalid MSIX offset for TIM LF %d", ring_id);
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return;
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}
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base = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
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tim_lf_unregister_irq(base, handle, msix_offset);
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}
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