caccf8b318
Change the prototype and the behavior of dev_ops->eth_mac_addr_set(): a return code is added to notify the caller (librte_ether) if an error occurred in the PMD. The new default MAC address is now copied in dev->data->mac_addrs[0] only if the operation is successful. The patch also updates all the PMDs accordingly. Signed-off-by: Olivier Matz <olivier.matz@6wind.com> Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru> Acked-by: Andrew Rybchenko <arybchenko@solarflare.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com> Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com> Acked-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
166 lines
5.8 KiB
C
166 lines
5.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2012 6WIND S.A.
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* Copyright 2012 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX4_H_
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#define RTE_PMD_MLX4_H_
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#include <net/if.h>
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#include <stdint.h>
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#include <sys/queue.h>
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/* Verbs headers do not support -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_ethdev_driver.h>
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#include <rte_ether.h>
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#include <rte_interrupts.h>
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#include <rte_mempool.h>
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#include <rte_spinlock.h>
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#ifndef IBV_RX_HASH_INNER
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/** This is not necessarily defined by supported RDMA core versions. */
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#define IBV_RX_HASH_INNER (1ull << 31)
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#endif /* IBV_RX_HASH_INNER */
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/** Maximum number of simultaneous MAC addresses. This value is arbitrary. */
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#define MLX4_MAX_MAC_ADDRESSES 128
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/** Request send completion once in every 64 sends, might be less. */
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#define MLX4_PMD_TX_PER_COMP_REQ 64
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/** Maximum size for inline data. */
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#define MLX4_PMD_MAX_INLINE 0
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/** Fixed RSS hash key size in bytes. Cannot be modified. */
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#define MLX4_RSS_HASH_KEY_SIZE 40
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/**
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* Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
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* from which buffers are to be transmitted will have to be mapped by this
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* driver to their own Memory Region (MR). This is a slow operation.
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*
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* This value is always 1 for RX queues.
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*/
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#ifndef MLX4_PMD_TX_MP_CACHE
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#define MLX4_PMD_TX_MP_CACHE 8
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#endif
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/** Interrupt alarm timeout value in microseconds. */
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#define MLX4_INTR_ALARM_TIMEOUT 100000
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/** Port parameter. */
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#define MLX4_PMD_PORT_KVARG "port"
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enum {
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PCI_VENDOR_ID_MELLANOX = 0x15b3,
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};
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enum {
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PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,
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PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,
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PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,
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};
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/** Driver name reported to lower layers and used in log output. */
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#define MLX4_DRIVER_NAME "net_mlx4"
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struct mlx4_drop;
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struct mlx4_rss;
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struct rxq;
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struct txq;
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struct rte_flow;
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/** Memory region descriptor. */
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struct mlx4_mr {
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LIST_ENTRY(mlx4_mr) next; /**< Next entry in list. */
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uintptr_t start; /**< Base address for memory region. */
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uintptr_t end; /**< End address for memory region. */
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uint32_t lkey; /**< L_Key extracted from @p mr. */
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uint32_t refcnt; /**< Reference count for this object. */
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struct priv *priv; /**< Back pointer to private data. */
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struct ibv_mr *mr; /**< Memory region associated with @p mp. */
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struct rte_mempool *mp; /**< Target memory pool (mempool). */
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};
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/** Private data structure. */
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struct priv {
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struct rte_eth_dev *dev; /**< Ethernet device. */
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struct ibv_context *ctx; /**< Verbs context. */
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struct ibv_device_attr device_attr; /**< Device properties. */
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struct ibv_pd *pd; /**< Protection Domain. */
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/* Device properties. */
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uint16_t mtu; /**< Configured MTU. */
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uint8_t port; /**< Physical port number. */
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uint32_t started:1; /**< Device started, flows enabled. */
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uint32_t vf:1; /**< This is a VF device. */
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uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */
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uint32_t isolated:1; /**< Toggle isolated mode. */
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uint32_t hw_csum:1; /**< Checksum offload is supported. */
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uint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */
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uint32_t hw_fcs_strip:1; /**< FCS stripping toggling is supported. */
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uint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */
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struct rte_intr_handle intr_handle; /**< Port interrupt handle. */
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struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */
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LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */
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LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
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LIST_HEAD(, mlx4_mr) mr; /**< Registered memory regions. */
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rte_spinlock_t mr_lock; /**< Lock for @p mr access. */
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struct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];
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/**< Configured MAC addresses. Unused entries are zeroed. */
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};
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/* mlx4_ethdev.c */
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int mlx4_get_ifname(const struct priv *priv, char (*ifname)[IF_NAMESIZE]);
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int mlx4_get_mac(struct priv *priv, uint8_t (*mac)[ETHER_ADDR_LEN]);
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int mlx4_mtu_get(struct priv *priv, uint16_t *mtu);
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int mlx4_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
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int mlx4_dev_set_link_down(struct rte_eth_dev *dev);
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int mlx4_dev_set_link_up(struct rte_eth_dev *dev);
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void mlx4_promiscuous_enable(struct rte_eth_dev *dev);
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void mlx4_promiscuous_disable(struct rte_eth_dev *dev);
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void mlx4_allmulticast_enable(struct rte_eth_dev *dev);
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void mlx4_allmulticast_disable(struct rte_eth_dev *dev);
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void mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
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int mlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
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uint32_t index, uint32_t vmdq);
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int mlx4_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
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int mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
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int mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
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void mlx4_stats_reset(struct rte_eth_dev *dev);
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void mlx4_dev_infos_get(struct rte_eth_dev *dev,
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struct rte_eth_dev_info *info);
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int mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete);
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int mlx4_flow_ctrl_get(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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int mlx4_flow_ctrl_set(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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const uint32_t *mlx4_dev_supported_ptypes_get(struct rte_eth_dev *dev);
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int mlx4_is_removed(struct rte_eth_dev *dev);
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/* mlx4_intr.c */
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int mlx4_intr_uninstall(struct priv *priv);
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int mlx4_intr_install(struct priv *priv);
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int mlx4_rxq_intr_enable(struct priv *priv);
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void mlx4_rxq_intr_disable(struct priv *priv);
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int mlx4_rx_intr_disable(struct rte_eth_dev *dev, uint16_t idx);
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int mlx4_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx);
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/* mlx4_mr.c */
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struct mlx4_mr *mlx4_mr_get(struct priv *priv, struct rte_mempool *mp);
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void mlx4_mr_put(struct mlx4_mr *mr);
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uint32_t mlx4_txq_add_mr(struct txq *txq, struct rte_mempool *mp,
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uint32_t i);
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#endif /* RTE_PMD_MLX4_H_ */
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