6094557de0
In case VIRTIO_F_ORDER_PLATFORM(36) is not negotiated, then the frontend and backend are assumed to be implemented in software, that is they can run on identical CPUs in an SMP configuration. Thus a weak form of memory barriers like rte_smp_r/wmb, other than rte_cio_r/wmb, is sufficient for this case(vq->hw->weak_barriers == 1) and yields better performance. For the above case, this patch helps yielding even better performance by replacing the two-way barriers with C11 one-way barriers for avail flags in packed ring. Meanwhile, a read barrier is required to ensure ordering between descriptor's flags and content reads [1]. With C11, load-acquire can enforce the ordering instead of rmb barrier. [1] https://patchwork.dpdk.org/patch/49109/ Signed-off-by: Joyce Kong <joyce.kong@arm.com> Reviewed-by: Gavin Hu <gavin.hu@arm.com> Reviewed-by: Phil Yang <phil.yang@arm.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com> |
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| .. | ||
| baseband | ||
| bus | ||
| common | ||
| compress | ||
| crypto | ||
| event | ||
| mempool | ||
| net | ||
| raw | ||
| Makefile | ||
| meson.build | ||