05fa3d4a65
Defined FPGA-BUS for Acceleration Drivers of AFUs 1. FPGA PCI Scan (1st Scan) follows DPDK UIO/VFIO PCI Scan Process, probe Intel FPGA Rawdev Driver, it will be covered in following patches. 2. AFU Scan(2nd Scan) bind DPDK driver to FPGA Partial-Bitstream. This scan is trigged by hotplug of IFPGA Rawdev probe, in this scan the AFUs will be created and their drivers are also probed. This patch will introduce rte_afu_device which describe the AFU device listed in the FPGA-BUS. Signed-off-by: Rosen Xu <rosen.xu@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
15 lines
389 B
Makefile
15 lines
389 B
Makefile
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright 2016 NXP
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include $(RTE_SDK)/mk/rte.vars.mk
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DIRS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += dpaa
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ifeq ($(CONFIG_RTE_EAL_VFIO),y)
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DIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc
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endif
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DIRS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += ifpga
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DIRS-$(CONFIG_RTE_LIBRTE_PCI_BUS) += pci
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DIRS-$(CONFIG_RTE_LIBRTE_VDEV_BUS) += vdev
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include $(RTE_SDK)/mk/rte.subdir.mk
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