23af667f15
Add API to program and manage hardware Layer 2 Table. L2T holds information necessary to rewrite specific fields in packet, such as destination MAC address and vlan id. Signed-off-by: Shagun Agrawal <shaguna@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Chelsio Communications.
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* All rights reserved.
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*/
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#ifndef _CXGBE_L2T_H_
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#define _CXGBE_L2T_H_
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#include "t4_msg.h"
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enum {
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L2T_SIZE = 4096 /* # of L2T entries */
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};
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enum {
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L2T_STATE_VALID, /* entry is up to date */
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L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */
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/* when state is one of the below the entry is not hashed */
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L2T_STATE_SWITCHING, /* entry is being used by a switching filter */
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L2T_STATE_UNUSED /* entry not in use */
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};
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/*
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* State for the corresponding entry of the HW L2 table.
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*/
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struct l2t_entry {
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u16 state; /* entry state */
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u16 idx; /* entry index within in-memory table */
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u16 vlan; /* VLAN TCI (id: bits 0-11, prio: 13-15 */
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u8 lport; /* destination port */
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u8 dmac[ETHER_ADDR_LEN]; /* destination MAC address */
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rte_spinlock_t lock; /* entry lock */
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rte_atomic32_t refcnt; /* entry reference count */
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};
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struct l2t_data {
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unsigned int l2t_start; /* start index of our piece of the L2T */
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unsigned int l2t_size; /* number of entries in l2tab */
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rte_rwlock_t lock; /* table rw lock */
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struct l2t_entry l2tab[0]; /* MUST BE LAST */
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};
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#define L2T_LPBK true
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#define L2T_ARPMISS true
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/* identifies sync vs async L2T_WRITE_REQs */
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#define S_SYNC_WR 12
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#define V_SYNC_WR(x) ((x) << S_SYNC_WR)
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#define F_SYNC_WR V_SYNC_WR(1)
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struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end);
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void t4_cleanup_l2t(struct adapter *adap);
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struct l2t_entry *cxgbe_l2t_alloc_switching(struct rte_eth_dev *dev, u16 vlan,
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u8 port, u8 *dmac);
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void cxgbe_l2t_release(struct l2t_entry *e);
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void do_l2t_write_rpl(struct adapter *p, const struct cpl_l2t_write_rpl *rpl);
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#endif /* _CXGBE_L2T_H_ */
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