66e0ea2c98
The NIC can have multiple PCIe links and can be attached to the multiple hosts, for example the same single NIC can be shared for multiple server units in the rack. On each PCIe link NIC can provide multiple PFs and VFs/SFs based on these ones. To provide the unambiguous identification of the PCIe function the controller index is added. The full representor identifier consists of three indices - controller index, PF index, and VF or SF index (if any). This patch introduces controller index to ethdev representor syntax, examples: [[c#]pf#]vf#: VF port representor/s, example: pf0vf1 [[c#]pf#]sf#: SF port representor/s, example: c1pf1sf[0-3] c# is controller(host) ID/range in case of multi-host, optional. For user application (e.g. OVS), PMD is responsible to interpret and locate representor device based on controller ID, PF ID and VF/SF ID in representor syntax. Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com> Acked-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
156 lines
4.0 KiB
C
156 lines
4.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Intel Corporation
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*/
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/**
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* @file Header file containing DPDK compilation parameters
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*
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* Header file containing DPDK compilation parameters. Also include the
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* meson-generated header file containing the detected parameters that
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* are variable across builds or build environments.
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*/
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#ifndef _RTE_CONFIG_H_
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#define _RTE_CONFIG_H_
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#include <rte_build_config.h>
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/* legacy defines */
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#ifdef RTE_EXEC_ENV_LINUX
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#define RTE_EXEC_ENV_LINUXAPP 1
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#endif
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#ifdef RTE_EXEC_ENV_FREEBSD
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#define RTE_EXEC_ENV_BSDAPP 1
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#endif
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/* String that appears before the version number */
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#define RTE_VER_PREFIX "DPDK"
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/****** library defines ********/
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/* EAL defines */
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#define RTE_MAX_HEAPS 32
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#define RTE_MAX_MEMSEG_LISTS 128
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#define RTE_MAX_MEMSEG_PER_LIST 8192
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#define RTE_MAX_MEM_MB_PER_LIST 32768
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#define RTE_MAX_MEMSEG_PER_TYPE 32768
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#define RTE_MAX_MEM_MB_PER_TYPE 65536
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#define RTE_MAX_MEMZONE 2560
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#define RTE_MAX_TAILQ 32
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#define RTE_LOG_DP_LEVEL RTE_LOG_INFO
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#define RTE_BACKTRACE 1
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#define RTE_MAX_VFIO_CONTAINERS 64
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/* bsd module defines */
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#define RTE_CONTIGMEM_MAX_NUM_BUFS 64
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#define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1
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#define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024)
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/* mempool defines */
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#define RTE_MEMPOOL_CACHE_MAX_SIZE 512
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/* mbuf defines */
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#define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc"
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#define RTE_MBUF_REFCNT_ATOMIC 1
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#define RTE_PKTMBUF_HEADROOM 128
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/* ether defines */
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#define RTE_MAX_QUEUES_PER_PORT 1024
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#define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 /* max 256 */
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#define RTE_ETHDEV_RXTX_CALLBACKS 1
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#define RTE_MAX_MULTI_HOST_CTRLS 4
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/* cryptodev defines */
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#define RTE_CRYPTO_MAX_DEVS 64
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#define RTE_CRYPTODEV_NAME_LEN 64
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#define RTE_CRYPTO_CALLBACKS 1
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/* compressdev defines */
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#define RTE_COMPRESS_MAX_DEVS 64
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/* regexdev defines */
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#define RTE_MAX_REGEXDEV_DEVS 32
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/* eventdev defines */
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#define RTE_EVENT_MAX_DEVS 16
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#define RTE_EVENT_MAX_QUEUES_PER_DEV 255
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#define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32
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#define RTE_EVENT_ETH_INTR_RING_SIZE 1024
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#define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32
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#define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32
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/* rawdev defines */
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#define RTE_RAWDEV_MAX_DEVS 64
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/* ip_fragmentation defines */
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#define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4
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#undef RTE_LIBRTE_IP_FRAG_TBL_STAT
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/* rte_power defines */
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#define RTE_MAX_LCORE_FREQS 64
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/* rte_sched defines */
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#undef RTE_SCHED_RED
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#undef RTE_SCHED_COLLECT_STATS
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#undef RTE_SCHED_SUBPORT_TC_OV
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#define RTE_SCHED_PORT_N_GRINDERS 8
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#undef RTE_SCHED_VECTOR
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/* KNI defines */
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#define RTE_KNI_PREEMPT_DEFAULT 1
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/* rte_graph defines */
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#define RTE_GRAPH_BURST_SIZE 256
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#define RTE_LIBRTE_GRAPH_STATS 1
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/****** driver defines ********/
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/* Packet prefetching in PMDs */
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#define RTE_PMD_PACKET_PREFETCH 1
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/* QuickAssist device */
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/* Max. number of QuickAssist devices which can be attached */
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#define RTE_PMD_QAT_MAX_PCI_DEVICES 48
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#define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
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#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
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/* virtio crypto defines */
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#define RTE_MAX_VIRTIO_CRYPTO 32
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/* DPAA SEC max cryptodev devices*/
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#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4
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/* fm10k defines */
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#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
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/* hns3 defines */
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#define RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF 256
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/* i40e defines */
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#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1
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#undef RTE_LIBRTE_I40E_16BYTE_RX_DESC
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#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64
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#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
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#define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4
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/* Ring net PMD settings */
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#define RTE_PMD_RING_MAX_RX_RINGS 16
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#define RTE_PMD_RING_MAX_TX_RINGS 16
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/* QEDE PMD defines */
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#define RTE_LIBRTE_QEDE_FW ""
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/* DLB PMD defines */
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#define RTE_LIBRTE_PMD_DLB_POLL_INTERVAL 1000
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#define RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE 0
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#undef RTE_LIBRTE_PMD_DLB_QUELL_STATS
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#define RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA 32
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/* DLB2 defines */
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#define RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL 1000
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#define RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE 0
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#undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
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#define RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA 32
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#define RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH 256
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#endif /* _RTE_CONFIG_H_ */
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