7906661eda
This is hw_atl logic layer derived from linux atlantic driver. It contains RX/TX hardware initialization sequences, various hw configuration. Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: Pavel Belous <pavel.belous@aquantia.com>
146 lines
4.4 KiB
C
146 lines
4.4 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
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/* Copyright (C) 2014-2017 aQuantia Corporation. */
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/* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific
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* constants.
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*/
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#ifndef HW_ATL_B0_INTERNAL_H
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#define HW_ATL_B0_INTERNAL_H
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#define HW_ATL_B0_MTU_JUMBO 16352U
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#define HW_ATL_B0_MTU 1514U
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#define HW_ATL_B0_TX_RINGS 4U
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#define HW_ATL_B0_RX_RINGS 4U
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#define HW_ATL_B0_RINGS_MAX 32U
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#define HW_ATL_B0_TXD_SIZE (16U)
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#define HW_ATL_B0_RXD_SIZE (16U)
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#define HW_ATL_B0_MAC 0U
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#define HW_ATL_B0_MAC_MIN 1U
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#define HW_ATL_B0_MAC_MAX 33U
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/* Maximum supported VLAN filters */
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#define HW_ATL_B0_MAX_VLAN_IDS 16
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/* UCAST/MCAST filters */
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#define HW_ATL_B0_UCAST_FILTERS_MAX 38
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#define HW_ATL_B0_MCAST_FILTERS_MAX 8
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/* interrupts */
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#define HW_ATL_B0_ERR_INT 8U
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#define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
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#define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
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#define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
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#define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
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#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
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#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
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#define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
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#define HW_ATL_B0_TXD_CTL_DD (0x00100000)
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#define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
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#define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000)
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#define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)
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#define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)
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#define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)
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#define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)
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#define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)
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#define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)
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#define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)
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#define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)
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#define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)
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#define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U
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#define HW_ATL_B0_MPI_STATE_ADR 0x036CU
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#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
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#define HW_ATL_B0_MPI_SPEED_SHIFT 16U
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#define HW_ATL_B0_TXBUF_MAX 160U
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#define HW_ATL_B0_RXBUF_MAX 320U
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#define HW_ATL_B0_RXD_BUF_SIZE_MAX (16 * 1024)
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#define HW_ATL_B0_RSS_REDIRECTION_MAX 64U
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#define HW_ATL_B0_RSS_REDIRECTION_BITS 3U
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#define HW_ATL_B0_RSS_HASHKEY_BITS 320U
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#define HW_ATL_B0_TCRSS_4_8 1
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#define HW_ATL_B0_TC_MAX 1U
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#define HW_ATL_B0_RSS_MAX 8U
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#define HW_ATL_B0_LRO_RXD_MAX 2U
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#define HW_ATL_B0_RS_SLIP_ENABLED 0U
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/* (256k -1(max pay_len) - 54(header)) */
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#define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U
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/* (256k -1(max pay_len) - 74(header)) */
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#define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U
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#define HW_ATL_B0_CHIP_REVISION_B0 0xA0U
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#define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU
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#define HW_ATL_B0_FW_SEMA_RAM 0x2U
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#define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00)
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#define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000)
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#define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007)
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#define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008)
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#define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0)
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#define HW_ATL_B0_TXC_CTL_CMD (0x00F00000)
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#define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000)
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#define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */
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#define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */
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#define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00)
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#define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000)
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#define HW_ATL_B0_RXD_DD (0x1)
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#define HW_ATL_B0_RXD_NCEA0 (0x1)
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#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)
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#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)
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#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)
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#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)
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#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)
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#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)
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#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)
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#define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C)
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#define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004)
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#define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008)
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#define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010)
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#define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0)
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#define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000)
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#define L2_FILTER_ACTION_DISCARD (0x0)
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#define L2_FILTER_ACTION_HOST (0x1)
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#define HW_ATL_B0_UCP_0X370_REG (0x370)
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#define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10)
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#define HW_ATL_INTR_MODER_MAX 0x1FF
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#define HW_ATL_INTR_MODER_MIN 0xFF
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#define HW_ATL_B0_MIN_RXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))
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#define HW_ATL_B0_MIN_TXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))
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#define HW_ATL_B0_MAX_RXD 8184U
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#define HW_ATL_B0_MAX_TXD 8184U
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/* HW layer capabilities */
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#endif /* HW_ATL_B0_INTERNAL_H */
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