1703e94ac5
This patch adds a PMD for the Intel Quick Assist Technology DH895xxC hardware accelerator. This patch depends on a QAT PF driver for device initialization. See the file docs/guides/cryptodevs/qat.rst for configuration details This patch supports a limited subset of QAT device functionality, currently supporting chaining of cipher and hash operations for the following algorithmsd: Cipher algorithms: - RTE_CRYPTO_CIPHER_AES_CBC (with 128-bit, 192-bit and 256-bit keys supported) Hash algorithms: - RTE_CRYPTO_AUTH_SHA1_HMAC - RTE_CRYPTO_AUTH_SHA256_HMAC - RTE_CRYPTO_AUTH_SHA512_HMAC - RTE_CRYPTO_AUTH_AES_XCBC_MAC Some limitation on this patchset which shall be contributed in a subsequent release: - Chained mbufs are not supported. - Hash only is not supported. - Cipher only is not supported. - Only in-place is currently supported (destination address is the same as source address). - Only supports session-oriented API implementation (session-less APIs are not supported). Signed-off-by: Declan Doherty <declan.doherty@intel.com> Signed-off-by: John Griffin <john.griffin@intel.com> Signed-off-by: Des O Dea <des.j.o.dea@intel.com> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com> Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
126 lines
4.5 KiB
C
126 lines
4.5 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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* Copyright(c) 2015 Intel Corporation.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* Contact Information:
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* qat-linux@intel.com
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*
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* BSD LICENSE
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* Copyright(c) 2015 Intel Corporation.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ICP_QAT_ALGS_H_
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#define _ICP_QAT_ALGS_H_
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#include <rte_memory.h>
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#include "icp_qat_hw.h"
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#include "icp_qat_fw.h"
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#include "icp_qat_fw_la.h"
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#define QAT_AES_HW_CONFIG_CBC_ENC(alg) \
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ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
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ICP_QAT_HW_CIPHER_NO_CONVERT, \
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ICP_QAT_HW_CIPHER_ENCRYPT)
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#define QAT_AES_HW_CONFIG_CBC_DEC(alg) \
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ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
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ICP_QAT_HW_CIPHER_KEY_CONVERT, \
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ICP_QAT_HW_CIPHER_DECRYPT)
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struct qat_alg_buf {
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uint32_t len;
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uint32_t resrvd;
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uint64_t addr;
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} __rte_packed;
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struct qat_alg_buf_list {
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uint64_t resrvd;
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uint32_t num_bufs;
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uint32_t num_mapped_bufs;
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struct qat_alg_buf bufers[];
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} __rte_packed __rte_cache_aligned;
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/* Common content descriptor */
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struct qat_alg_cd {
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struct icp_qat_hw_cipher_algo_blk cipher;
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struct icp_qat_hw_auth_algo_blk hash;
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} __rte_packed __rte_cache_aligned;
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struct qat_session {
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enum icp_qat_fw_la_cmd_id qat_cmd;
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enum icp_qat_hw_cipher_algo qat_cipher_alg;
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enum icp_qat_hw_cipher_dir qat_dir;
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enum icp_qat_hw_cipher_mode qat_mode;
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enum icp_qat_hw_auth_algo qat_hash_alg;
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struct qat_alg_cd cd;
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phys_addr_t cd_paddr;
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struct icp_qat_fw_la_bulk_req fw_req;
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struct qat_crypto_instance *inst;
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uint8_t salt[ICP_QAT_HW_AES_BLK_SZ];
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rte_spinlock_t lock; /* protects this struct */
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};
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struct qat_alg_ablkcipher_cd {
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struct icp_qat_hw_cipher_algo_blk *cd;
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phys_addr_t cd_paddr;
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struct icp_qat_fw_la_bulk_req fw_req;
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struct qat_crypto_instance *inst;
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rte_spinlock_t lock; /* protects this struct */
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};
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int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);
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int qat_alg_aead_session_create_content_desc(struct qat_session *cd,
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uint8_t *enckey, uint32_t enckeylen,
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uint8_t *authkey, uint32_t authkeylen,
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uint32_t add_auth_data_length,
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uint32_t digestsize);
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void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);
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void qat_alg_ablkcipher_init_enc(struct qat_alg_ablkcipher_cd *cd,
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int alg, const uint8_t *key,
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unsigned int keylen);
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void qat_alg_ablkcipher_init_dec(struct qat_alg_ablkcipher_cd *cd,
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int alg, const uint8_t *key,
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unsigned int keylen);
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int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
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#endif
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