7d3b1ec47f
This is to logically group unit tests into their own folder, separating them from "app" folder. Hopefully this will make the unit test in DPDK more visible. Following binaries moved to "test" folder: cmdline-test test-acl test-pipeline test <-- various DPDK unit tests Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
278 lines
8.1 KiB
C
278 lines
8.1 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <rte_log.h>
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#include <rte_ethdev.h>
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#include <rte_ether.h>
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#include <rte_ip.h>
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#include <rte_byteorder.h>
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#include <rte_port_ring.h>
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#include <rte_table_acl.h>
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#include <rte_pipeline.h>
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#include "main.h"
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enum {
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PROTO_FIELD_IPV4,
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SRC_FIELD_IPV4,
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DST_FIELD_IPV4,
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SRCP_FIELD_IPV4,
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DSTP_FIELD_IPV4,
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NUM_FIELDS_IPV4
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};
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/*
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* Here we define the 'shape' of the data we're searching for,
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* by defining the meta-data of the ACL rules.
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* in this case, we're defining 5 tuples. IP addresses, ports,
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* and protocol.
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*/
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struct rte_acl_field_def ipv4_field_formats[NUM_FIELDS_IPV4] = {
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{
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.type = RTE_ACL_FIELD_TYPE_BITMASK,
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.size = sizeof(uint8_t),
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.field_index = PROTO_FIELD_IPV4,
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.input_index = PROTO_FIELD_IPV4,
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.offset = sizeof(struct ether_hdr) +
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offsetof(struct ipv4_hdr, next_proto_id),
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},
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{
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.type = RTE_ACL_FIELD_TYPE_MASK,
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.size = sizeof(uint32_t),
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.field_index = SRC_FIELD_IPV4,
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.input_index = SRC_FIELD_IPV4,
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.offset = sizeof(struct ether_hdr) +
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offsetof(struct ipv4_hdr, src_addr),
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},
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{
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.type = RTE_ACL_FIELD_TYPE_MASK,
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.size = sizeof(uint32_t),
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.field_index = DST_FIELD_IPV4,
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.input_index = DST_FIELD_IPV4,
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.offset = sizeof(struct ether_hdr) +
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offsetof(struct ipv4_hdr, dst_addr),
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},
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{
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.type = RTE_ACL_FIELD_TYPE_RANGE,
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.size = sizeof(uint16_t),
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.field_index = SRCP_FIELD_IPV4,
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.input_index = SRCP_FIELD_IPV4,
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.offset = sizeof(struct ether_hdr) + sizeof(struct ipv4_hdr),
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},
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{
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.type = RTE_ACL_FIELD_TYPE_RANGE,
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.size = sizeof(uint16_t),
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.field_index = DSTP_FIELD_IPV4,
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.input_index = SRCP_FIELD_IPV4,
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.offset = sizeof(struct ether_hdr) + sizeof(struct ipv4_hdr) +
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sizeof(uint16_t),
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},
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};
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void
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app_main_loop_worker_pipeline_acl(void) {
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struct rte_pipeline_params pipeline_params = {
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.name = "pipeline",
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.socket_id = rte_socket_id(),
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};
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struct rte_pipeline *p;
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uint32_t port_in_id[APP_MAX_PORTS];
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uint32_t port_out_id[APP_MAX_PORTS];
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uint32_t table_id;
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uint32_t i;
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RTE_LOG(INFO, USER1,
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"Core %u is doing work (pipeline with ACL table)\n",
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rte_lcore_id());
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/* Pipeline configuration */
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p = rte_pipeline_create(&pipeline_params);
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if (p == NULL)
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rte_panic("Unable to configure the pipeline\n");
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/* Input port configuration */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_port_ring_reader_params port_ring_params = {
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.ring = app.rings_rx[i],
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};
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struct rte_pipeline_port_in_params port_params = {
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.ops = &rte_port_ring_reader_ops,
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.arg_create = (void *) &port_ring_params,
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.f_action = NULL,
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.arg_ah = NULL,
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.burst_size = app.burst_size_worker_read,
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};
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if (rte_pipeline_port_in_create(p, &port_params,
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&port_in_id[i]))
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rte_panic("Unable to configure input port for "
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"ring %d\n", i);
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}
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/* Output port configuration */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_port_ring_writer_params port_ring_params = {
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.ring = app.rings_tx[i],
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.tx_burst_sz = app.burst_size_worker_write,
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};
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struct rte_pipeline_port_out_params port_params = {
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.ops = &rte_port_ring_writer_ops,
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.arg_create = (void *) &port_ring_params,
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.f_action = NULL,
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.arg_ah = NULL,
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};
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if (rte_pipeline_port_out_create(p, &port_params,
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&port_out_id[i]))
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rte_panic("Unable to configure output port for "
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"ring %d\n", i);
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}
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/* Table configuration */
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{
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struct rte_table_acl_params table_acl_params = {
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.name = "test", /* unique identifier for acl contexts */
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.n_rules = 1 << 5,
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.n_rule_fields = DIM(ipv4_field_formats),
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};
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/* Copy in the rule meta-data defined above into the params */
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memcpy(table_acl_params.field_format, ipv4_field_formats,
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sizeof(ipv4_field_formats));
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struct rte_pipeline_table_params table_params = {
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.ops = &rte_table_acl_ops,
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.arg_create = &table_acl_params,
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.f_action_hit = NULL,
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.f_action_miss = NULL,
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.arg_ah = NULL,
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.action_data_size = 0,
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};
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if (rte_pipeline_table_create(p, &table_params, &table_id))
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rte_panic("Unable to configure the ACL table\n");
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}
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/* Interconnecting ports and tables */
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for (i = 0; i < app.n_ports; i++)
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if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
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table_id))
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rte_panic("Unable to connect input port %u to "
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"table %u\n", port_in_id[i], table_id);
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/* Add entries to tables */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_pipeline_table_entry table_entry = {
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.action = RTE_PIPELINE_ACTION_PORT,
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{.port_id = port_out_id[i & (app.n_ports - 1)]},
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};
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struct rte_table_acl_rule_add_params rule_params;
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struct rte_pipeline_table_entry *entry_ptr;
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int key_found, ret;
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memset(&rule_params, 0, sizeof(rule_params));
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/* Set the rule values */
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rule_params.field_value[SRC_FIELD_IPV4].value.u32 = 0;
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rule_params.field_value[SRC_FIELD_IPV4].mask_range.u32 = 0;
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rule_params.field_value[DST_FIELD_IPV4].value.u32 =
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i << (24 - __builtin_popcount(app.n_ports - 1));
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rule_params.field_value[DST_FIELD_IPV4].mask_range.u32 =
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8 + __builtin_popcount(app.n_ports - 1);
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rule_params.field_value[SRCP_FIELD_IPV4].value.u16 = 0;
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rule_params.field_value[SRCP_FIELD_IPV4].mask_range.u16 =
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UINT16_MAX;
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rule_params.field_value[DSTP_FIELD_IPV4].value.u16 = 0;
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rule_params.field_value[DSTP_FIELD_IPV4].mask_range.u16 =
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UINT16_MAX;
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rule_params.field_value[PROTO_FIELD_IPV4].value.u8 = 0;
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rule_params.field_value[PROTO_FIELD_IPV4].mask_range.u8 = 0;
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rule_params.priority = 0;
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uint32_t dst_addr = rule_params.field_value[DST_FIELD_IPV4].
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value.u32;
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uint32_t dst_mask =
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rule_params.field_value[DST_FIELD_IPV4].mask_range.u32;
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printf("Adding rule to ACL table (IPv4 destination = "
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"%u.%u.%u.%u/%u => port out = %u)\n",
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(dst_addr & 0xFF000000) >> 24,
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(dst_addr & 0x00FF0000) >> 16,
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(dst_addr & 0x0000FF00) >> 8,
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dst_addr & 0x000000FF,
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dst_mask,
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table_entry.port_id);
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/* For ACL, add needs an rte_table_acl_rule_add_params struct */
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ret = rte_pipeline_table_entry_add(p, table_id, &rule_params,
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&table_entry, &key_found, &entry_ptr);
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if (ret < 0)
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rte_panic("Unable to add entry to table %u (%d)\n",
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table_id, ret);
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}
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/* Enable input ports */
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for (i = 0; i < app.n_ports; i++)
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if (rte_pipeline_port_in_enable(p, port_in_id[i]))
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rte_panic("Unable to enable input port %u\n",
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port_in_id[i]);
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/* Check pipeline consistency */
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if (rte_pipeline_check(p) < 0)
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rte_panic("Pipeline consistency check failed\n");
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/* Run-time */
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#if APP_FLUSH == 0
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for ( ; ; )
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rte_pipeline_run(p);
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#else
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for (i = 0; ; i++) {
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rte_pipeline_run(p);
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if ((i & APP_FLUSH) == 0)
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rte_pipeline_flush(p);
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}
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#endif
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}
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