847d97894b
Implement TIR modification (see mlx5_devx_cmd_modify_tir()) using DevX API. TIR is the object containing the hashed table of Rx queue. The functionality to configure/modify this HW-related object is prerequisite to implement rete_flow_shared_action_update() for shared RSS action in mlx5 PMD. HW-related structures for TIR modification add in mlx5_prm.h. Signed-off-by: Andrey Vesnovaty <andreyv@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
97 lines
2.0 KiB
Plaintext
97 lines
2.0 KiB
Plaintext
INTERNAL {
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global:
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mlx5_common_init;
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mlx5_common_verbs_reg_mr;
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mlx5_common_verbs_dereg_mr;
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mlx5_create_mr_ext;
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mlx5_dev_to_pci_addr;
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mlx5_devx_cmd_create_cq;
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mlx5_devx_cmd_create_flex_parser;
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mlx5_devx_cmd_create_qp;
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mlx5_devx_cmd_create_rq;
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mlx5_devx_cmd_create_rqt;
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mlx5_devx_cmd_create_sq;
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mlx5_devx_cmd_create_tir;
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mlx5_devx_cmd_create_td;
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mlx5_devx_cmd_create_tis;
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mlx5_devx_cmd_create_virtio_q_counters;
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mlx5_devx_cmd_create_virtq;
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mlx5_devx_cmd_destroy;
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mlx5_devx_cmd_flow_counter_alloc;
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mlx5_devx_cmd_flow_counter_query;
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mlx5_devx_cmd_flow_dump;
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mlx5_devx_cmd_mkey_create;
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mlx5_devx_cmd_modify_qp_state;
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mlx5_devx_cmd_modify_rq;
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mlx5_devx_cmd_modify_rqt;
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mlx5_devx_cmd_modify_sq;
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mlx5_devx_cmd_modify_tir;
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mlx5_devx_cmd_modify_virtq;
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mlx5_devx_cmd_qp_query_tis_td;
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mlx5_devx_cmd_query_hca_attr;
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mlx5_devx_cmd_query_parse_samples;
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mlx5_devx_cmd_query_virtio_q_counters;
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mlx5_devx_cmd_query_virtq;
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mlx5_devx_cmd_register_read;
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mlx5_devx_get_out_command_status;
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mlx5_get_ifname_sysfs;
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mlx5_get_dbr;
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mlx5_mp_init_primary;
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mlx5_mp_uninit_primary;
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mlx5_mp_init_secondary;
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mlx5_mp_uninit_secondary;
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mlx5_mp_req_mr_create;
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mlx5_mp_req_queue_state_modify;
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mlx5_mp_req_verbs_cmd_fd;
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mlx5_mr_btree_init;
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mlx5_mr_btree_free;
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mlx5_mr_btree_dump;
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mlx5_mr_addr2mr_bh;
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mlx5_mr_release_cache;
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mlx5_mr_dump_cache;
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mlx5_mr_rebuild_cache;
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mlx5_mr_insert_cache;
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mlx5_mr_lookup_cache;
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mlx5_mr_lookup_list;
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mlx5_mr_create_primary;
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mlx5_mr_flush_local_cache;
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mlx5_nl_allmulti;
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mlx5_nl_devlink_family_id_get;
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mlx5_nl_driver_reload;
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mlx5_nl_enable_roce_get;
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mlx5_nl_enable_roce_set;
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mlx5_nl_ifindex;
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mlx5_nl_init;
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mlx5_nl_mac_addr_add;
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mlx5_nl_mac_addr_flush;
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mlx5_nl_mac_addr_remove;
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mlx5_nl_mac_addr_sync;
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mlx5_nl_portnum;
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mlx5_nl_promisc;
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mlx5_nl_switch_info;
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mlx5_nl_vf_mac_addr_modify;
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mlx5_nl_vlan_vmwa_create;
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mlx5_nl_vlan_vmwa_delete;
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mlx5_release_dbr;
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mlx5_translate_port_name;
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mlx5_malloc_mem_select;
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mlx5_memory_stat_dump;
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mlx5_malloc;
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mlx5_realloc;
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mlx5_free;
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mlx5_pci_driver_register;
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};
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