d00fa50779
With this change, DPAA and DPAA2 configuration compiled applications are interoperable without any impact on the functional behavior. Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
24 lines
604 B
Plaintext
24 lines
604 B
Plaintext
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright 2016 Freescale Semiconductor, Inc.
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# Copyright 2017 NXP
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#include "defconfig_arm64-armv8a-linuxapp-gcc"
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# NXP (Freescale) - Soc Architecture with FMAN, QMAN & BMAN support
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CONFIG_RTE_MACHINE="dpaa"
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CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72"
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CONFIG_RTE_LIBRTE_VHOST_NUMA=n
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CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
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#
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# Compile Environment Abstraction Layer
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#
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CONFIG_RTE_MAX_LCORE=16
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CONFIG_RTE_MAX_NUMA_NODES=1
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CONFIG_RTE_CACHE_LINE_SIZE=64
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CONFIG_RTE_PKTMBUF_HEADROOM=128
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# NXP DPAA Bus
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CONFIG_RTE_LIBRTE_DPAA_DEBUG_DRIVER=n
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CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n
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