29631ee5c8
Add all necessary elements for DPDK to compile and run EAL on LoongArch64 Soc. This includes: - EAL library implementation for LoongArch ISA. - meson build structure for 'loongarch' architecture. RTE_ARCH_LOONGARCH define is added for architecture identification. - xmm_t structure operation stubs as there is no vector support in the current version for LoongArch. Compilation was tested on Debian and CentOS using loongarch64 cross-compile toolchain from x86 build hosts. Functions were tested on Loongnix and Kylin which are two Linux distributions supported LoongArch host based on Linux 4.19 maintained by Loongson Corporation. We also tested DPDK on LoongArch with some external applications, including: Pktgen-DPDK, OVS, VPP. The platform is currently marked as linux-only because there is no other OS than Linux support LoongArch host currently. The i40e PMD driver is disabled on LoongArch because of the absence of vector support in the current version. Similar to RISC-V, the compilation of following modules has been disabled by this commit and will be re-enabled in later commits as fixes are introduced: net/ixgbe, net/memif, net/tap, example/l3fwd. Signed-off-by: Min Zhou <zhoumin@loongson.cn>
83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015 Cavium, Inc
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* Copyright(c) 2022 StarFive
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* Copyright(c) 2022 SiFive
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* Copyright(c) 2022 Semihalf
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*/
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#ifndef _TEST_XMMT_OPS_H_
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#define _TEST_XMMT_OPS_H_
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#include <rte_vect.h>
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#if defined(RTE_ARCH_ARM)
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/* vect_* abstraction implementation using NEON */
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/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
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#define vect_loadu_sil128(p) vld1q_s32((const int32_t *)p)
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/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
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static __rte_always_inline xmm_t
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vect_set_epi32(int i3, int i2, int i1, int i0)
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{
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int32_t data[4] = {i0, i1, i2, i3};
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return vld1q_s32(data);
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}
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#elif defined(RTE_ARCH_X86)
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/* vect_* abstraction implementation using SSE */
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/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
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#define vect_loadu_sil128(p) _mm_loadu_si128(p)
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/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
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#define vect_set_epi32(i3, i2, i1, i0) _mm_set_epi32(i3, i2, i1, i0)
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#elif defined(RTE_ARCH_PPC_64)
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/* vect_* abstraction implementation using ALTIVEC */
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/* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/
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#define vect_loadu_sil128(p) vec_ld(0, p)
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/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
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static __rte_always_inline xmm_t
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vect_set_epi32(int i3, int i2, int i1, int i0)
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{
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xmm_t data = (xmm_t){i0, i1, i2, i3};
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return data;
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}
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#elif defined(RTE_ARCH_RISCV)
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#define vect_loadu_sil128(p) vect_load_128(p)
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/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
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static __rte_always_inline xmm_t
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vect_set_epi32(int i3, int i2, int i1, int i0)
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{
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xmm_t data = (xmm_t){i0, i1, i2, i3};
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return data;
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}
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#elif defined(RTE_ARCH_LOONGARCH)
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#define vect_loadu_sil128(p) vect_load_128(p)
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/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
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static __rte_always_inline xmm_t
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vect_set_epi32(int i3, int i2, int i1, int i0)
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{
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xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3}};
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return data;
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}
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#endif
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#endif /* _TEST_XMMT_OPS_H_ */
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