48f31ca50c
This application is purposefully built to benchmark the performance of the Intel DPDK Packet Framework toolbox. It uses 3 CPU cores connected in a chain through SW rings (NICs --> Core A --> Core B --> Core C --> NICs) 1. Core A: reads packets from NIC ports and writes them to SW queues; 2. Core B: instantiates a Packet Framework pipeline that uses ring reader input ports, a table whose type is selected trhough command line arguments (--none, --stub, --lpm, --acl, --hash[-spec]-KEYSZ-TYPE, with KEYSZ as 8, 16 or 32 bytes and TYPE as ext (Extendible bucket) or lru (LRU)) and ring writers output ports; 3. Core C: reads packets from SW rings and writes them to NIC ports. Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com> Acked-by: Pablo de Lara Guarch <pablo.de.lara.guarch@intel.com> Acked by: Ivan Boule <ivan.boule@6wind.com> [Thomas: remove dedicated build option]
197 lines
5.7 KiB
C
197 lines
5.7 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <rte_log.h>
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#include <rte_ethdev.h>
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#include <rte_ether.h>
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#include <rte_ip.h>
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#include <rte_byteorder.h>
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#include <rte_port_ring.h>
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#include <rte_table_lpm.h>
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#include <rte_pipeline.h>
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#include "main.h"
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void
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app_main_loop_worker_pipeline_lpm(void) {
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struct rte_pipeline_params pipeline_params = {
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.name = "pipeline",
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.socket_id = rte_socket_id(),
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};
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struct rte_pipeline *p;
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uint32_t port_in_id[APP_MAX_PORTS];
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uint32_t port_out_id[APP_MAX_PORTS];
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uint32_t table_id;
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uint32_t i;
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RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with "
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"LPM table)\n", rte_lcore_id());
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/* Pipeline configuration */
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p = rte_pipeline_create(&pipeline_params);
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if (p == NULL)
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rte_panic("Unable to configure the pipeline\n");
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/* Input port configuration */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_port_ring_reader_params port_ring_params = {
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.ring = app.rings_rx[i],
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};
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struct rte_pipeline_port_in_params port_params = {
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.ops = &rte_port_ring_reader_ops,
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.arg_create = (void *) &port_ring_params,
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.f_action = NULL,
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.arg_ah = NULL,
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.burst_size = app.burst_size_worker_read,
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};
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if (rte_pipeline_port_in_create(p, &port_params,
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&port_in_id[i]))
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rte_panic("Unable to configure input port for "
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"ring %d\n", i);
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}
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/* Output port configuration */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_port_ring_writer_params port_ring_params = {
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.ring = app.rings_tx[i],
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.tx_burst_sz = app.burst_size_worker_write,
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};
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struct rte_pipeline_port_out_params port_params = {
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.ops = &rte_port_ring_writer_ops,
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.arg_create = (void *) &port_ring_params,
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.f_action = NULL,
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.f_action_bulk = NULL,
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.arg_ah = NULL,
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};
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if (rte_pipeline_port_out_create(p, &port_params,
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&port_out_id[i]))
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rte_panic("Unable to configure output port for "
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"ring %d\n", i);
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}
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/* Table configuration */
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{
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struct rte_table_lpm_params table_lpm_params = {
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.n_rules = 1 << 24,
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.entry_unique_size =
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sizeof(struct rte_pipeline_table_entry),
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.offset = 32,
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};
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struct rte_pipeline_table_params table_params = {
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.ops = &rte_table_lpm_ops,
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.arg_create = &table_lpm_params,
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.f_action_hit = NULL,
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.f_action_miss = NULL,
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.arg_ah = NULL,
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.action_data_size = 0,
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};
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if (rte_pipeline_table_create(p, &table_params, &table_id))
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rte_panic("Unable to configure the LPM table\n");
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}
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/* Interconnecting ports and tables */
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for (i = 0; i < app.n_ports; i++)
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if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
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table_id))
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rte_panic("Unable to connect input port %u to "
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"table %u\n", port_in_id[i], table_id);
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/* Add entries to tables */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_pipeline_table_entry entry = {
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.action = RTE_PIPELINE_ACTION_PORT,
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{.port_id = port_out_id[i & (app.n_ports - 1)]},
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};
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struct rte_table_lpm_key key = {
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.ip = i << (24 - __builtin_popcount(app.n_ports - 1)),
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.depth = 8 + __builtin_popcount(app.n_ports - 1),
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};
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struct rte_pipeline_table_entry *entry_ptr;
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int key_found, status;
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printf("Adding rule to LPM table (IPv4 destination = %"
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PRIu32 ".%" PRIu32 ".%" PRIu32 ".%" PRIu32 "/%" PRIu8
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" => port out = %" PRIu32 ")\n",
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(key.ip & 0xFF000000) >> 24,
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(key.ip & 0x00FF0000) >> 16,
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(key.ip & 0x0000FF00) >> 8,
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key.ip & 0x000000FF,
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key.depth,
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i);
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status = rte_pipeline_table_entry_add(p, table_id, &key, &entry,
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&key_found, &entry_ptr);
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if (status < 0)
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rte_panic("Unable to add entry to table %u (%d)\n",
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table_id, status);
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}
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/* Enable input ports */
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for (i = 0; i < app.n_ports; i++)
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if (rte_pipeline_port_in_enable(p, port_in_id[i]))
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rte_panic("Unable to enable input port %u\n",
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port_in_id[i]);
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/* Check pipeline consistency */
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if (rte_pipeline_check(p) < 0)
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rte_panic("Pipeline consistency check failed\n");
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/* Run-time */
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#if APP_FLUSH == 0
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for ( ; ; )
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rte_pipeline_run(p);
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#else
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for (i = 0; ; i++) {
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rte_pipeline_run(p);
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if ((i & APP_FLUSH) == 0)
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rte_pipeline_flush(p);
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}
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#endif
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}
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