711baf1c2a
Add queue start and stop operations. Tx queue needs to update the flow control value, Which will be added in sub subsequent patch. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
362 lines
10 KiB
C
362 lines
10 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef __OTX2_ETHDEV_H__
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#define __OTX2_ETHDEV_H__
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#include <stdint.h>
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#include <rte_common.h>
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#include <rte_ethdev.h>
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#include <rte_kvargs.h>
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#include <rte_mbuf.h>
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#include <rte_mempool.h>
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#include <rte_string_fns.h>
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#include "otx2_common.h"
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#include "otx2_dev.h"
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#include "otx2_irq.h"
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#include "otx2_mempool.h"
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#include "otx2_rx.h"
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#include "otx2_tx.h"
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#define OTX2_ETH_DEV_PMD_VERSION "1.0"
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/* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
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/* Minimum CQ size should be 4K */
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#define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
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#define otx2_ethdev_fixup_is_min_4k_q(dev) \
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((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
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/* Limit CQ being full */
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#define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
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#define otx2_ethdev_fixup_is_limit_cq_full(dev) \
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((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
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/* Used for struct otx2_eth_dev::flags */
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#define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
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/* VLAN tag inserted by NIX_TX_VTAG_ACTION.
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* In Tx space is always reserved for this in FRS.
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*/
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#define NIX_MAX_VTAG_INS 2
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#define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
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/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
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#define NIX_L2_OVERHEAD \
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(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
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/* HW config of frame size doesn't include FCS */
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#define NIX_MAX_HW_FRS 9212
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#define NIX_MIN_HW_FRS 60
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/* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
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#define NIX_MAX_FRS \
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(NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
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#define NIX_MIN_FRS \
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(NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
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#define NIX_MAX_MTU \
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(NIX_MAX_FRS - NIX_L2_OVERHEAD)
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#define NIX_MAX_SQB 512
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#define NIX_MIN_SQB 32
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#define NIX_SQB_LIST_SPACE 2
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#define NIX_RSS_RETA_SIZE_MAX 256
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/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
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#define NIX_RSS_GRPS 8
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#define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
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#define NIX_RSS_RETA_SIZE 64
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#define NIX_RX_MIN_DESC 16
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#define NIX_RX_MIN_DESC_ALIGN 16
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#define NIX_RX_NB_SEG_MAX 6
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#define NIX_CQ_ENTRY_SZ 128
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#define NIX_CQ_ALIGN 512
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#define NIX_SQB_LOWER_THRESH 90
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#define LMT_SLOT_MASK 0x7f
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/* If PTP is enabled additional SEND MEM DESC is required which
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* takes 2 words, hence max 7 iova address are possible
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*/
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#if defined(RTE_LIBRTE_IEEE1588)
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#define NIX_TX_NB_SEG_MAX 7
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#else
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#define NIX_TX_NB_SEG_MAX 9
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#endif
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#define CQ_OP_STAT_OP_ERR 63
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#define CQ_OP_STAT_CQ_ERR 46
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#define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
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#define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
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#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
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ETH_RSS_TCP | ETH_RSS_SCTP | \
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ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
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#define NIX_TX_OFFLOAD_CAPA ( \
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DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
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DEV_TX_OFFLOAD_MT_LOCKFREE | \
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DEV_TX_OFFLOAD_VLAN_INSERT | \
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DEV_TX_OFFLOAD_QINQ_INSERT | \
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_SCTP_CKSUM | \
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DEV_TX_OFFLOAD_MULTI_SEGS | \
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DEV_TX_OFFLOAD_IPV4_CKSUM)
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#define NIX_RX_OFFLOAD_CAPA ( \
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DEV_RX_OFFLOAD_CHECKSUM | \
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DEV_RX_OFFLOAD_SCTP_CKSUM | \
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DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
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DEV_RX_OFFLOAD_SCATTER | \
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DEV_RX_OFFLOAD_JUMBO_FRAME | \
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DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_RX_OFFLOAD_VLAN_STRIP | \
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DEV_RX_OFFLOAD_VLAN_FILTER | \
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DEV_RX_OFFLOAD_QINQ_STRIP | \
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DEV_RX_OFFLOAD_TIMESTAMP)
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#define NIX_DEFAULT_RSS_CTX_GROUP 0
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#define NIX_DEFAULT_RSS_MCAM_IDX -1
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enum nix_q_size_e {
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nix_q_size_16, /* 16 entries */
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nix_q_size_64, /* 64 entries */
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nix_q_size_256,
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nix_q_size_1K,
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nix_q_size_4K,
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nix_q_size_16K,
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nix_q_size_64K,
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nix_q_size_256K,
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nix_q_size_1M, /* Million entries */
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nix_q_size_max
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};
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struct otx2_qint {
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struct rte_eth_dev *eth_dev;
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uint8_t qintx;
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};
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struct otx2_rss_info {
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uint64_t nix_rss;
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uint32_t flowkey_cfg;
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uint16_t rss_size;
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uint8_t rss_grps;
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uint8_t alg_idx; /* Selected algo index */
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uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
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uint8_t key[NIX_HASH_KEY_SIZE];
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};
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struct otx2_eth_qconf {
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union {
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struct rte_eth_txconf tx;
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struct rte_eth_rxconf rx;
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} conf;
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void *mempool;
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uint32_t socket_id;
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uint16_t nb_desc;
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};
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struct otx2_npc_flow_info {
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uint16_t channel; /*rx channel */
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uint16_t flow_prealloc_size;
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uint16_t flow_max_priority;
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};
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struct otx2_eth_dev {
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OTX2_DEV; /* Base class */
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MARKER otx2_eth_dev_data_start;
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uint16_t sqb_size;
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uint16_t rx_chan_base;
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uint16_t tx_chan_base;
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uint8_t rx_chan_cnt;
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uint8_t tx_chan_cnt;
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uint8_t lso_tsov4_idx;
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uint8_t lso_tsov6_idx;
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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uint8_t max_mac_entries;
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uint8_t lf_tx_stats;
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uint8_t lf_rx_stats;
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uint16_t flags;
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uint16_t cints;
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uint16_t qints;
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uint8_t configured;
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uint8_t configured_qints;
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uint8_t configured_nb_rx_qs;
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uint8_t configured_nb_tx_qs;
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uint16_t nix_msixoff;
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uintptr_t base;
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uintptr_t lmt_addr;
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uint16_t scalar_ena;
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uint16_t max_sqb_count;
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uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
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uint64_t rx_offloads;
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uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
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uint64_t tx_offloads;
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uint64_t rx_offload_capa;
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uint64_t tx_offload_capa;
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struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
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struct otx2_rss_info rss_info;
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uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
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uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
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struct otx2_npc_flow_info npc_flow;
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struct otx2_eth_qconf *tx_qconf;
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struct otx2_eth_qconf *rx_qconf;
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struct rte_eth_dev *eth_dev;
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} __rte_cache_aligned;
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struct otx2_eth_txq {
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uint64_t cmd[8];
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int64_t fc_cache_pkts;
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uint64_t *fc_mem;
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void *lmt_addr;
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rte_iova_t io_addr;
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rte_iova_t fc_iova;
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uint16_t sqes_per_sqb_log2;
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int16_t nb_sqb_bufs_adj;
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MARKER slow_path_start;
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uint16_t nb_sqb_bufs;
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uint16_t sq;
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uint64_t offloads;
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struct otx2_eth_dev *dev;
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struct rte_mempool *sqb_pool;
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struct otx2_eth_qconf qconf;
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} __rte_cache_aligned;
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struct otx2_eth_rxq {
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uint64_t mbuf_initializer;
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uint64_t data_off;
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uintptr_t desc;
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void *lookup_mem;
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uintptr_t cq_door;
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uint64_t wdata;
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int64_t *cq_status;
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uint32_t head;
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uint32_t qmask;
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uint32_t available;
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uint16_t rq;
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struct otx2_timesync_info *tstamp;
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MARKER slow_path_start;
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uint64_t aura;
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uint64_t offloads;
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uint32_t qlen;
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struct rte_mempool *pool;
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enum nix_q_size_e qsize;
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struct rte_eth_dev *eth_dev;
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struct otx2_eth_qconf qconf;
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} __rte_cache_aligned;
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static inline struct otx2_eth_dev *
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otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
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{
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return eth_dev->data->dev_private;
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}
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/* Ops */
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void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_dev_info *dev_info);
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void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
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void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
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void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
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void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
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void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
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int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
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int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
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uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
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/* Link */
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void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
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int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
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void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
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struct cgx_link_user_info *link);
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/* IRQ */
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int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
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int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
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void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
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void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
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/* Debug */
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int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
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int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
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struct rte_dev_reg_info *regs);
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int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
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void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
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/* Stats */
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int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_stats *stats);
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void otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
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int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
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uint16_t queue_id, uint8_t stat_idx,
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uint8_t is_rx);
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int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_xstat *xstats, unsigned int n);
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int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
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struct rte_eth_xstat_name *xstats_names,
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unsigned int limit);
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void otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
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int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
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const uint64_t *ids,
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uint64_t *values, unsigned int n);
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int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
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struct rte_eth_xstat_name *xstats_names,
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const uint64_t *ids, unsigned int limit);
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/* RSS */
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void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
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uint8_t *key, uint32_t key_len);
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uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
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uint64_t ethdev_rss, uint8_t rss_level);
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int otx2_rss_set_hf(struct otx2_eth_dev *dev,
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uint32_t flowkey_cfg, uint8_t *alg_idx,
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uint8_t group, int mcam_index);
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int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
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uint16_t *ind_tbl);
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int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
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int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size);
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int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size);
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int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_conf *rss_conf);
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int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_conf *rss_conf);
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/* CGX */
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int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
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int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
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int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
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struct rte_ether_addr *addr);
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/* Mac address handling */
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int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
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struct rte_ether_addr *addr);
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int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
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int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
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struct rte_ether_addr *addr,
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uint32_t index, uint32_t pool);
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void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
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int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
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/* Devargs */
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int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
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struct otx2_eth_dev *dev);
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/* Rx and Tx routines */
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void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
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#endif /* __OTX2_ETHDEV_H__ */
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