200df241d4
Before the device PTP hardware clock can be initialized, some steps must be taken by the driver. This includes writing some registers and initializing the PHY. Some of these steps are distinct depending on the device type (E810 or E822). Additionally, a future change will introduce more steps for E822 devices to program the Clock Generation Unit. Introduce ice_ptp_init_phc as well as device-specific sub-functions for e810 and e822 devices. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Junfeng Guo <junfeng.guo@intel.com>
118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2021 Intel Corporation
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*/
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#ifndef _ICE_CGU_REGS_H_
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#define _ICE_CGU_REGS_H_
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#define NAC_CGU_DWORD9 0x24
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union nac_cgu_dword9 {
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struct {
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u32 time_ref_freq_sel : 3;
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u32 clk_eref1_en : 1;
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u32 clk_eref0_en : 1;
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u32 time_ref_en : 1;
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u32 time_sync_en : 1;
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u32 one_pps_out_en : 1;
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u32 clk_ref_synce_en : 1;
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u32 clk_synce1_en : 1;
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u32 clk_synce0_en : 1;
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u32 net_clk_ref1_en : 1;
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u32 net_clk_ref0_en : 1;
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u32 clk_synce1_amp : 2;
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u32 misc6 : 1;
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u32 clk_synce0_amp : 2;
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u32 one_pps_out_amp : 2;
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u32 misc24 : 12;
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} field;
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u32 val;
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};
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#define NAC_CGU_DWORD19 0x4c
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union nac_cgu_dword19 {
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struct {
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u32 tspll_fbdiv_intgr : 8;
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u32 fdpll_ulck_thr : 5;
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u32 misc15 : 3;
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u32 tspll_ndivratio : 4;
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u32 tspll_iref_ndivratio : 3;
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u32 misc19 : 1;
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u32 japll_ndivratio : 4;
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u32 japll_iref_ndivratio : 3;
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u32 misc27 : 1;
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} field;
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u32 val;
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};
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#define NAC_CGU_DWORD22 0x58
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union nac_cgu_dword22 {
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struct {
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u32 fdpll_frac_div_out_nc : 2;
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u32 fdpll_lock_int_for : 1;
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u32 synce_hdov_int_for : 1;
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u32 synce_lock_int_for : 1;
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u32 fdpll_phlead_slip_nc : 1;
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u32 fdpll_acc1_ovfl_nc : 1;
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u32 fdpll_acc2_ovfl_nc : 1;
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u32 synce_status_nc : 6;
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u32 fdpll_acc1f_ovfl : 1;
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u32 misc18 : 1;
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u32 fdpllclk_div : 4;
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u32 time1588clk_div : 4;
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u32 synceclk_div : 4;
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u32 synceclk_sel_div2 : 1;
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u32 fdpllclk_sel_div2 : 1;
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u32 time1588clk_sel_div2 : 1;
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u32 misc3 : 1;
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} field;
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u32 val;
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};
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#define NAC_CGU_DWORD24 0x60
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union nac_cgu_dword24 {
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struct {
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u32 tspll_fbdiv_frac : 22;
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u32 misc20 : 2;
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u32 ts_pll_enable : 1;
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u32 time_sync_tspll_align_sel : 1;
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u32 ext_synce_sel : 1;
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u32 ref1588_ck_div : 4;
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u32 time_ref_sel : 1;
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} field;
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u32 val;
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};
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#define TSPLL_CNTR_BIST_SETTINGS 0x344
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union tspll_cntr_bist_settings {
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struct {
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u32 i_irefgen_settling_time_cntr_7_0 : 8;
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u32 i_irefgen_settling_time_ro_standby_1_0 : 2;
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u32 reserved195 : 5;
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u32 i_plllock_sel_0 : 1;
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u32 i_plllock_sel_1 : 1;
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u32 i_plllock_cnt_6_0 : 7;
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u32 i_plllock_cnt_10_7 : 4;
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u32 reserved200 : 4;
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} field;
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u32 val;
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};
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#define TSPLL_RO_BWM_LF 0x370
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union tspll_ro_bwm_lf {
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struct {
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u32 bw_freqov_high_cri_7_0 : 8;
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u32 bw_freqov_high_cri_9_8 : 2;
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u32 biascaldone_cri : 1;
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u32 plllock_gain_tran_cri : 1;
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u32 plllock_true_lock_cri : 1;
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u32 pllunlock_flag_cri : 1;
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u32 afcerr_cri : 1;
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u32 afcdone_cri : 1;
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u32 feedfwrdgain_cal_cri_7_0 : 8;
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u32 m2fbdivmod_cri_7_0 : 8;
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} field;
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u32 val;
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};
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#endif /* _ICE_CGU_REGS_H_ */
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