3998e2a072
Replace the BSD license header with the SPDX tag for files with only an Intel copyright on them. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
352 lines
8.5 KiB
C
352 lines
8.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2014 Intel Corporation
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*/
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#ifndef _MAIN_H_
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#define _MAIN_H_
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/* Logical cores */
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#ifndef APP_MAX_SOCKETS
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#define APP_MAX_SOCKETS 2
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#endif
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#ifndef APP_MAX_LCORES
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#define APP_MAX_LCORES RTE_MAX_LCORE
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#endif
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#ifndef APP_MAX_NIC_PORTS
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#define APP_MAX_NIC_PORTS RTE_MAX_ETHPORTS
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#endif
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#ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT
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#define APP_MAX_RX_QUEUES_PER_NIC_PORT 128
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#endif
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#ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT
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#define APP_MAX_TX_QUEUES_PER_NIC_PORT 128
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#endif
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#ifndef APP_MAX_IO_LCORES
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#if (APP_MAX_LCORES > 16)
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#define APP_MAX_IO_LCORES 16
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#else
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#define APP_MAX_IO_LCORES APP_MAX_LCORES
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#endif
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#endif
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#if (APP_MAX_IO_LCORES > APP_MAX_LCORES)
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#error "APP_MAX_IO_LCORES is too big"
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#endif
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#ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE
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#define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16
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#endif
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#ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE
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#define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16
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#endif
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#if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)
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#error "APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big"
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#endif
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#ifndef APP_MAX_WORKER_LCORES
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#if (APP_MAX_LCORES > 16)
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#define APP_MAX_WORKER_LCORES 16
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#else
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#define APP_MAX_WORKER_LCORES APP_MAX_LCORES
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#endif
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#endif
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#if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)
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#error "APP_MAX_WORKER_LCORES is too big"
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#endif
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/* Mempools */
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#ifndef APP_DEFAULT_MBUF_DATA_SIZE
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#define APP_DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
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#endif
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#ifndef APP_DEFAULT_MEMPOOL_BUFFERS
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#define APP_DEFAULT_MEMPOOL_BUFFERS 8192 * 4
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#endif
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#ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE
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#define APP_DEFAULT_MEMPOOL_CACHE_SIZE 256
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#endif
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/* LPM Tables */
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#ifndef APP_MAX_LPM_RULES
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#define APP_MAX_LPM_RULES 1024
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#endif
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/* NIC RX */
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#ifndef APP_DEFAULT_NIC_RX_RING_SIZE
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#define APP_DEFAULT_NIC_RX_RING_SIZE 1024
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#endif
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/*
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* RX and TX Prefetch, Host, and Write-back threshold values should be
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* carefully set for optimal performance. Consult the network
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* controller's datasheet and supporting DPDK documentation for guidance
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* on how these parameters should be set.
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*/
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#ifndef APP_DEFAULT_NIC_RX_PTHRESH
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#define APP_DEFAULT_NIC_RX_PTHRESH 8
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#endif
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#ifndef APP_DEFAULT_NIC_RX_HTHRESH
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#define APP_DEFAULT_NIC_RX_HTHRESH 8
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#endif
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#ifndef APP_DEFAULT_NIC_RX_WTHRESH
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#define APP_DEFAULT_NIC_RX_WTHRESH 4
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#endif
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#ifndef APP_DEFAULT_NIC_RX_FREE_THRESH
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#define APP_DEFAULT_NIC_RX_FREE_THRESH 64
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#endif
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#ifndef APP_DEFAULT_NIC_RX_DROP_EN
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#define APP_DEFAULT_NIC_RX_DROP_EN 0
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#endif
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/* NIC TX */
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#ifndef APP_DEFAULT_NIC_TX_RING_SIZE
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#define APP_DEFAULT_NIC_TX_RING_SIZE 1024
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#endif
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/*
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* These default values are optimized for use with the Intel(R) 82599 10 GbE
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* Controller and the DPDK ixgbe PMD. Consider using other values for other
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* network controllers and/or network drivers.
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*/
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#ifndef APP_DEFAULT_NIC_TX_PTHRESH
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#define APP_DEFAULT_NIC_TX_PTHRESH 36
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#endif
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#ifndef APP_DEFAULT_NIC_TX_HTHRESH
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#define APP_DEFAULT_NIC_TX_HTHRESH 0
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#endif
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#ifndef APP_DEFAULT_NIC_TX_WTHRESH
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#define APP_DEFAULT_NIC_TX_WTHRESH 0
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#endif
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#ifndef APP_DEFAULT_NIC_TX_FREE_THRESH
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#define APP_DEFAULT_NIC_TX_FREE_THRESH 0
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#endif
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#ifndef APP_DEFAULT_NIC_TX_RS_THRESH
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#define APP_DEFAULT_NIC_TX_RS_THRESH 0
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#endif
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/* Software Rings */
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#ifndef APP_DEFAULT_RING_RX_SIZE
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#define APP_DEFAULT_RING_RX_SIZE 1024
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#endif
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#ifndef APP_DEFAULT_RING_TX_SIZE
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#define APP_DEFAULT_RING_TX_SIZE 1024
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#endif
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/* Bursts */
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#ifndef APP_MBUF_ARRAY_SIZE
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#define APP_MBUF_ARRAY_SIZE 512
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#endif
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#ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ
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#define APP_DEFAULT_BURST_SIZE_IO_RX_READ 144
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#endif
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#if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)
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#error "APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big"
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#endif
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#ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE
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#define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE 144
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#endif
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#if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)
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#error "APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big"
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#endif
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#ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ
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#define APP_DEFAULT_BURST_SIZE_IO_TX_READ 144
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#endif
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#if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)
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#error "APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big"
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#endif
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#ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE
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#define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE 144
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#endif
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#if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)
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#error "APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big"
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#endif
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#ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ
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#define APP_DEFAULT_BURST_SIZE_WORKER_READ 144
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#endif
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#if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)
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#error "APP_DEFAULT_BURST_SIZE_WORKER_READ is too big"
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#endif
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#ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE
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#define APP_DEFAULT_BURST_SIZE_WORKER_WRITE 144
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#endif
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#if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)
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#error "APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big"
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#endif
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/* Load balancing logic */
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#ifndef APP_DEFAULT_IO_RX_LB_POS
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#define APP_DEFAULT_IO_RX_LB_POS 29
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#endif
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#if (APP_DEFAULT_IO_RX_LB_POS >= 64)
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#error "APP_DEFAULT_IO_RX_LB_POS is too big"
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#endif
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struct app_mbuf_array {
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struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
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uint32_t n_mbufs;
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};
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enum app_lcore_type {
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e_APP_LCORE_DISABLED = 0,
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e_APP_LCORE_IO,
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e_APP_LCORE_WORKER
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};
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struct app_lcore_params_io {
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/* I/O RX */
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struct {
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/* NIC */
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struct {
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uint16_t port;
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uint8_t queue;
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} nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
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uint32_t n_nic_queues;
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/* Rings */
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struct rte_ring *rings[APP_MAX_WORKER_LCORES];
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uint32_t n_rings;
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/* Internal buffers */
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struct app_mbuf_array mbuf_in;
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struct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];
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uint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];
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/* Stats */
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uint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
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uint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
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uint32_t rings_count[APP_MAX_WORKER_LCORES];
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uint32_t rings_iters[APP_MAX_WORKER_LCORES];
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} rx;
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/* I/O TX */
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struct {
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/* Rings */
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struct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
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/* NIC */
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uint16_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
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uint32_t n_nic_ports;
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/* Internal buffers */
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struct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
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uint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
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/* Stats */
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uint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
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uint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
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uint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
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uint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
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} tx;
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};
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struct app_lcore_params_worker {
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/* Rings */
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struct rte_ring *rings_in[APP_MAX_IO_LCORES];
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uint32_t n_rings_in;
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struct rte_ring *rings_out[APP_MAX_NIC_PORTS];
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/* LPM table */
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struct rte_lpm *lpm_table;
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uint32_t worker_id;
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/* Internal buffers */
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struct app_mbuf_array mbuf_in;
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struct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];
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uint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];
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/* Stats */
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uint32_t rings_in_count[APP_MAX_IO_LCORES];
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uint32_t rings_in_iters[APP_MAX_IO_LCORES];
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uint32_t rings_out_count[APP_MAX_NIC_PORTS];
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uint32_t rings_out_iters[APP_MAX_NIC_PORTS];
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};
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struct app_lcore_params {
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union {
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struct app_lcore_params_io io;
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struct app_lcore_params_worker worker;
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};
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enum app_lcore_type type;
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struct rte_mempool *pool;
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} __rte_cache_aligned;
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struct app_lpm_rule {
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uint32_t ip;
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uint8_t depth;
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uint8_t if_out;
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};
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struct app_params {
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/* lcore */
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struct app_lcore_params lcore_params[APP_MAX_LCORES];
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/* NIC */
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uint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];
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uint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];
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/* mbuf pools */
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struct rte_mempool *pools[APP_MAX_SOCKETS];
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/* LPM tables */
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struct rte_lpm *lpm_tables[APP_MAX_SOCKETS];
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struct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];
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uint32_t n_lpm_rules;
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/* rings */
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uint32_t nic_rx_ring_size;
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uint32_t nic_tx_ring_size;
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uint32_t ring_rx_size;
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uint32_t ring_tx_size;
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/* burst size */
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uint32_t burst_size_io_rx_read;
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uint32_t burst_size_io_rx_write;
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uint32_t burst_size_io_tx_read;
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uint32_t burst_size_io_tx_write;
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uint32_t burst_size_worker_read;
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uint32_t burst_size_worker_write;
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/* load balancing */
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uint8_t pos_lb;
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} __rte_cache_aligned;
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extern struct app_params app;
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int app_parse_args(int argc, char **argv);
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void app_print_usage(void);
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void app_init(void);
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int app_lcore_main_loop(void *arg);
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int app_get_nic_rx_queues_per_port(uint16_t port);
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int app_get_lcore_for_nic_rx(uint16_t port, uint8_t queue,
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uint32_t *lcore_out);
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int app_get_lcore_for_nic_tx(uint16_t port, uint32_t *lcore_out);
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int app_is_socket_used(uint32_t socket);
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uint32_t app_get_lcores_io_rx(void);
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uint32_t app_get_lcores_worker(void);
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void app_print_params(void);
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#endif /* _MAIN_H_ */
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