7483341ae5
Currently, most ethdev callback API use queue ID as parameter, but Rx and Tx queue release callback use queue object which is used by Rx and Tx burst data plane callback. To align with other eth device queue configuration callbacks: - queue release callbacks are changed to use queue ID - all drivers are adapted Signed-off-by: Xueming Li <xuemingl@nvidia.com> Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Acked-by: Somnath Kotur <somnath.kotur@broadcom.com> Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
195 lines
5.6 KiB
C
195 lines
5.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
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* Copyright(c) 2018 Synopsys, Inc. All rights reserved.
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*/
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#ifndef _AXGBE_RXTX_H_
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#define _AXGBE_RXTX_H_
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/* to suppress gcc warnings related to descriptor casting*/
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#ifdef RTE_TOOLCHAIN_GCC
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#pragma GCC diagnostic ignored "-Wcast-qual"
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#endif
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#ifdef RTE_TOOLCHAIN_CLANG
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#pragma GCC diagnostic ignored "-Wcast-qual"
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#endif
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/* Descriptor related defines */
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#define AXGBE_MAX_RING_DESC 4096 /*should be power of 2*/
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#define AXGBE_TX_DESC_MIN_FREE (AXGBE_MAX_RING_DESC >> 3)
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#define AXGBE_TX_DESC_MAX_PROC (AXGBE_MAX_RING_DESC >> 1)
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#define AXGBE_MIN_RING_DESC 32
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#define RTE_AXGBE_DESCS_PER_LOOP 4
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#define RTE_AXGBE_MAX_RX_BURST 32
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#define AXGBE_RX_FREE_THRESH 32
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#define AXGBE_TX_FREE_THRESH 32
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#define AXGBE_DESC_ALIGN 128
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#define AXGBE_DESC_OWN 0x80000000
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#define AXGBE_ERR_STATUS 0x000f0000
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#define AXGBE_L3_CSUM_ERR 0x00050000
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#define AXGBE_L4_CSUM_ERR 0x00060000
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#include "axgbe_common.h"
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#define AXGBE_GET_DESC_PT(_queue, _idx) \
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(((_queue)->desc) + \
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((_idx) & ((_queue)->nb_desc - 1)))
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#define AXGBE_GET_DESC_IDX(_queue, _idx) \
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((_idx) & ((_queue)->nb_desc - 1)) \
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/* Rx desc format */
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union axgbe_rx_desc {
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struct {
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uint64_t baddr;
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uint32_t desc2;
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uint32_t desc3;
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} read;
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struct {
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uint32_t desc0;
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uint32_t desc1;
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uint32_t desc2;
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uint32_t desc3;
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} write;
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};
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struct axgbe_rx_queue {
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/* membuf pool for rx buffers */
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struct rte_mempool *mb_pool;
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/* H/w Rx buffer size configured in DMA */
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unsigned int buf_size;
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/* CRC h/w offload */
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uint16_t crc_len;
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/* address of s/w rx buffers */
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struct rte_mbuf **sw_ring;
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/* Port private data */
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struct axgbe_port *pdata;
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/* Number of Rx descriptors in queue */
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uint16_t nb_desc;
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/* max free RX desc to hold */
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uint16_t free_thresh;
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/* Index of descriptor to check for packet availability */
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uint64_t cur;
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/* Index of descriptor to check for buffer reallocation */
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uint64_t dirty;
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/* Software Rx descriptor ring*/
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volatile union axgbe_rx_desc *desc;
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/* Ring physical address */
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uint64_t ring_phys_addr;
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/* Dma Channel register address */
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void *dma_regs;
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/* Dma channel tail register address*/
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volatile uint32_t *dma_tail_reg;
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/* DPDK queue index */
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uint16_t queue_id;
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/* dpdk port id*/
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uint16_t port_id;
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/* queue stats */
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uint64_t pkts;
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uint64_t bytes;
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uint64_t errors;
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uint64_t rx_mbuf_alloc_failed;
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/* Number of mbufs allocated from pool*/
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uint64_t mbuf_alloc;
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} __rte_cache_aligned;
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/*Tx descriptor format */
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struct axgbe_tx_desc {
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phys_addr_t baddr;
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uint32_t desc2;
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uint32_t desc3;
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};
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struct axgbe_tx_queue {
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/* Port private data reference */
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struct axgbe_port *pdata;
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/* Number of Tx descriptors in queue*/
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uint16_t nb_desc;
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/* Start freeing TX buffers if there are less free descriptors than
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* this value
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*/
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uint16_t free_thresh;
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/* Available descriptors for Tx processing*/
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uint16_t nb_desc_free;
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/* Batch of mbufs/descs to release */
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uint16_t free_batch_cnt;
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/* Flag for vector support */
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uint16_t vector_disable;
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/* Index of descriptor to be used for current transfer */
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uint64_t cur;
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/* Index of descriptor to check for transfer complete */
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uint64_t dirty;
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/* Virtual address of ring */
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volatile struct axgbe_tx_desc *desc;
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/* Physical address of ring */
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uint64_t ring_phys_addr;
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/* Dma channel register space */
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void *dma_regs;
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/* Dma tail register address of ring*/
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volatile uint32_t *dma_tail_reg;
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/* Tx queue index/id*/
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uint16_t queue_id;
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/* Reference to hold Tx mbufs mapped to Tx descriptors freed
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* after transmission confirmation
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*/
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struct rte_mbuf **sw_ring;
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/* dpdk port id*/
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uint16_t port_id;
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/* queue stats */
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uint64_t pkts;
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uint64_t bytes;
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uint64_t errors;
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} __rte_cache_aligned;
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/*Queue related APIs */
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/*
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* RX/TX function prototypes
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*/
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void axgbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx);
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int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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void axgbe_dev_enable_tx(struct rte_eth_dev *dev);
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void axgbe_dev_disable_tx(struct rte_eth_dev *dev);
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int axgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int axgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int axgbe_dev_fw_version_get(struct rte_eth_dev *eth_dev,
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char *fw_version, size_t fw_size);
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uint16_t axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t axgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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void axgbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx);
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int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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void axgbe_dev_enable_rx(struct rte_eth_dev *dev);
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void axgbe_dev_disable_rx(struct rte_eth_dev *dev);
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int axgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int axgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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uint16_t axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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uint16_t axgbe_recv_pkts_threshold_refresh(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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void axgbe_dev_clear_queues(struct rte_eth_dev *dev);
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int axgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
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int axgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
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#endif /* _AXGBE_RXTX_H_ */
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