63d5d0af4f
LS1088 platform CENA operation are causing issues at high load. CINH (cache inhibited) mode is working fine with minor performance impact. This patch enables CINH mode selectively on LS1088 platform Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2016 NXP
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*
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*/
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#ifndef _DPAA2_HW_DPIO_H_
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#define _DPAA2_HW_DPIO_H_
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#include <mc/fsl_dpio.h>
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#include <mc/fsl_mc_sys.h>
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struct dpaa2_io_portal_t {
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struct dpaa2_dpio_dev *dpio_dev;
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struct dpaa2_dpio_dev *ethrx_dpio_dev;
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uint64_t net_tid;
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uint64_t sec_tid;
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void *eventdev;
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};
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/*! Global per thread DPIO portal */
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RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
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#define DPAA2_PER_LCORE_DPIO RTE_PER_LCORE(_dpaa2_io).dpio_dev
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#define DPAA2_PER_LCORE_PORTAL DPAA2_PER_LCORE_DPIO->sw_portal
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#define DPAA2_PER_LCORE_ETHRX_DPIO RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
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#define DPAA2_PER_LCORE_ETHRX_PORTAL DPAA2_PER_LCORE_ETHRX_DPIO->sw_portal
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/* Variable to store DPAA2 DQRR size */
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extern uint8_t dpaa2_dqrr_size;
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/* Variable to store DPAA2 EQCR size */
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extern uint8_t dpaa2_eqcr_size;
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extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
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/* Affine a DPIO portal to current processing thread */
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int dpaa2_affine_qbman_swp(void);
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/* Affine additional DPIO portal to current crypto processing thread */
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int dpaa2_affine_qbman_ethrx_swp(void);
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/* allocate memory for FQ - dq storage */
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int
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dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage);
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/* free memory for FQ- dq storage */
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void
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dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage);
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/* free the enqueue response descriptors */
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uint32_t
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dpaa2_free_eq_descriptors(void);
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#endif /* _DPAA2_HW_DPIO_H_ */
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