2c0784eb88
Add support to configure drop action in rte_flow infrastructure and add counter for dropped packets due to this filter action "rx_gft_filter_drop". Also, update supported flows and actions in qede guide. Signed-off-by: Shahed Shaikh <shshaikh@marvell.com>
309 lines
8.9 KiB
C
309 lines
8.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2016 - 2018 Cavium Inc.
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* All rights reserved.
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* www.cavium.com
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*/
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#ifndef _QEDE_ETHDEV_H_
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#define _QEDE_ETHDEV_H_
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#include <sys/queue.h>
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#include <rte_ether.h>
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#include <rte_ethdev_driver.h>
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#include <rte_ethdev_pci.h>
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#include <rte_dev.h>
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#include <rte_ip.h>
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/* ecore includes */
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#include "base/bcm_osal.h"
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#include "base/ecore.h"
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#include "base/ecore_dev_api.h"
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#include "base/ecore_l2_api.h"
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#include "base/ecore_vf_api.h"
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#include "base/ecore_hsi_common.h"
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#include "base/ecore_int_api.h"
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#include "base/ecore_chain.h"
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#include "base/ecore_status.h"
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#include "base/ecore_hsi_eth.h"
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#include "base/ecore_iov_api.h"
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#include "base/ecore_cxt.h"
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#include "base/nvm_cfg.h"
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#include "base/ecore_sp_commands.h"
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#include "base/ecore_l2.h"
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#include "base/ecore_vf.h"
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#include "qede_logs.h"
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#include "qede_if.h"
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#include "qede_rxtx.h"
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#define qede_stringify1(x...) #x
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#define qede_stringify(x...) qede_stringify1(x)
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/* Driver versions */
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#define QEDE_PMD_VER_PREFIX "QEDE PMD"
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#define QEDE_PMD_VERSION_MAJOR 2
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#define QEDE_PMD_VERSION_MINOR 10
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#define QEDE_PMD_VERSION_REVISION 0
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#define QEDE_PMD_VERSION_PATCH 1
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#define QEDE_PMD_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "." \
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qede_stringify(QEDE_PMD_VERSION_MINOR) "." \
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qede_stringify(QEDE_PMD_VERSION_REVISION) "." \
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qede_stringify(QEDE_PMD_VERSION_PATCH)
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#define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE
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#define QEDE_PMD_VER_PREFIX "QEDE PMD"
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#define QEDE_RSS_INDIR_INITED (1 << 0)
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#define QEDE_RSS_KEY_INITED (1 << 1)
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#define QEDE_RSS_CAPS_INITED (1 << 2)
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#define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
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#define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues * \
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(edev)->dev_info.num_tc)
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#define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues)
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#define QEDE_RSS_COUNT(dev) ((dev)->data->nb_rx_queues)
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#define QEDE_TSS_COUNT(dev) ((dev)->data->nb_tx_queues)
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#define QEDE_DUPLEX_FULL 1
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#define QEDE_DUPLEX_HALF 2
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#define QEDE_DUPLEX_UNKNOWN 0xff
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#define QEDE_SUPPORTED_AUTONEG (1 << 6)
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#define QEDE_SUPPORTED_PAUSE (1 << 13)
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#define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private)
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#define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev)
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#define QEDE_INIT(eth_dev) { \
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struct qede_dev *qdev = eth_dev->data->dev_private; \
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struct ecore_dev *edev = &qdev->edev; \
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}
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/************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/
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#define PCI_VENDOR_ID_QLOGIC 0x1077
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#define CHIP_NUM_57980E 0x1634
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#define CHIP_NUM_57980S 0x1629
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#define CHIP_NUM_VF 0x1630
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#define CHIP_NUM_57980S_40 0x1634
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#define CHIP_NUM_57980S_25 0x1656
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#define CHIP_NUM_57980S_IOV 0x1664
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#define CHIP_NUM_57980S_100 0x1644
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#define CHIP_NUM_57980S_50 0x1654
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#define CHIP_NUM_AH_50G 0x8070
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#define CHIP_NUM_AH_10G 0x8071
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#define CHIP_NUM_AH_40G 0x8072
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#define CHIP_NUM_AH_25G 0x8073
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#define CHIP_NUM_AH_IOV 0x8090
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#define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E
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#define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S
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#define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF
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#define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40
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#define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25
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#define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV
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#define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100
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#define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50
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#define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G
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#define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G
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#define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G
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#define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G
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#define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV
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extern char qede_fw_file[];
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/* Number of PF connections - 32 RX + 32 TX */
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#define QEDE_PF_NUM_CONNS (64)
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/* Maximum number of flowdir filters */
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#define QEDE_RFS_MAX_FLTR (256)
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#define QEDE_MAX_MCAST_FILTERS (64)
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enum qed_filter_rx_mode_type {
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QED_FILTER_RX_MODE_TYPE_REGULAR,
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QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC,
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QED_FILTER_RX_MODE_TYPE_PROMISC,
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};
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struct qede_vlan_entry {
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SLIST_ENTRY(qede_vlan_entry) list;
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uint16_t vid;
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};
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struct qede_mcast_entry {
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struct rte_ether_addr mac;
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SLIST_ENTRY(qede_mcast_entry) list;
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};
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struct qede_ucast_entry {
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struct rte_ether_addr mac;
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uint16_t vlan;
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uint16_t vni;
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SLIST_ENTRY(qede_ucast_entry) list;
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};
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#ifndef IPV6_ADDR_LEN
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#define IPV6_ADDR_LEN (16)
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#endif
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struct qede_arfs_tuple {
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union {
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uint32_t src_ipv4;
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uint8_t src_ipv6[IPV6_ADDR_LEN];
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};
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union {
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uint32_t dst_ipv4;
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uint8_t dst_ipv6[IPV6_ADDR_LEN];
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};
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uint16_t src_port;
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uint16_t dst_port;
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uint16_t eth_proto;
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uint8_t ip_proto;
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/* Describe filtering mode needed for this kind of filter */
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enum ecore_filter_config_mode mode;
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};
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struct qede_arfs_entry {
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uint32_t soft_id; /* unused for now */
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uint16_t pkt_len; /* actual packet length to match */
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uint16_t rx_queue; /* queue to be steered to */
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bool is_drop; /* drop action */
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const struct rte_memzone *mz; /* mz used to hold L2 frame */
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struct qede_arfs_tuple tuple;
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SLIST_ENTRY(qede_arfs_entry) list;
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};
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/* Opaque handle for rte flow managed by PMD */
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struct rte_flow {
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struct qede_arfs_entry entry;
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};
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struct qede_arfs_info {
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struct ecore_arfs_config_params arfs;
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uint16_t filter_count;
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SLIST_HEAD(arfs_list_head, qede_arfs_entry)arfs_list_head;
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};
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/* IANA assigned default UDP ports for encapsulation protocols */
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#define QEDE_VXLAN_DEF_PORT (4789)
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#define QEDE_GENEVE_DEF_PORT (6081)
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struct qede_tunn_params {
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bool enable;
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uint16_t num_filters;
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uint16_t filter_type;
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uint16_t udp_port;
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};
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/*
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* Structure to store private data for each port.
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*/
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struct qede_dev {
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struct ecore_dev edev;
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const struct qed_eth_ops *ops;
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struct qed_dev_eth_info dev_info;
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struct ecore_sb_info *sb_array;
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struct qede_fastpath *fp_array;
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struct qede_fastpath_cmt *fp_array_cmt;
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uint16_t mtu;
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bool enable_tx_switching;
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bool rss_enable;
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struct rte_eth_rss_conf rss_conf;
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uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];
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uint64_t rss_hf;
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uint8_t rss_key_len;
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bool enable_lro;
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uint8_t num_rx_queues;
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uint8_t num_tx_queues;
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SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head;
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uint16_t configured_vlans;
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bool accept_any_vlan;
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struct rte_ether_addr primary_mac;
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SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head;
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uint16_t num_mc_addr;
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SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head;
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uint16_t num_uc_addr;
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bool handle_hw_err;
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struct qede_tunn_params vxlan;
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struct qede_tunn_params geneve;
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struct qede_tunn_params ipgre;
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struct qede_arfs_info arfs_info;
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bool vlan_strip_flg;
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char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
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bool vport_started;
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int vlan_offload_mask;
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void *ethdev;
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};
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static inline void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
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{
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memset(ucast, 0, sizeof(struct ecore_filter_ucast));
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ucast->is_rx_filter = true;
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ucast->is_tx_filter = true;
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/* ucast->assert_on_error = true; - For debug */
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}
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/* Non-static functions */
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int qede_config_rss(struct rte_eth_dev *eth_dev);
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int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_conf *rss_conf);
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int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
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struct rte_eth_rss_reta_entry64 *reta_conf,
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uint16_t reta_size);
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int qed_fill_eth_dev_info(struct ecore_dev *edev,
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struct qed_dev_eth_info *info);
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int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up);
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int qede_link_update(struct rte_eth_dev *eth_dev,
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__rte_unused int wait_to_complete);
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int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type,
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enum rte_filter_op op, void *arg);
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int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev,
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enum rte_filter_op filter_op, void *arg);
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int qede_check_fdir_support(struct rte_eth_dev *eth_dev);
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uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev,
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struct rte_eth_fdir_filter *fdir,
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void *buff,
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struct ecore_arfs_config_params *params);
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void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev);
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int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg);
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int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu);
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int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg);
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int qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
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struct rte_eth_udp_tunnel *tunnel_udp);
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int qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
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struct rte_eth_udp_tunnel *tunnel_udp);
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enum _ecore_status_t
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qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
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bool add);
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void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg);
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int qede_ucast_filter(struct rte_eth_dev *eth_dev,
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struct ecore_filter_ucast *ucast,
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bool add);
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#endif /* _QEDE_ETHDEV_H_ */
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