ce6427ddca
The new macro __rte_cold, for compiler hinting, is now used where appropriate for consistency. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
893 lines
25 KiB
C
893 lines
25 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2013-2015 Intel Corporation
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*/
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#include <inttypes.h>
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#include <rte_ethdev_driver.h>
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#include <rte_common.h>
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#include "fm10k.h"
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#include "base/fm10k_type.h"
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#include <tmmintrin.h>
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#ifndef __INTEL_COMPILER
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#pragma GCC diagnostic ignored "-Wcast-qual"
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#endif
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static void
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fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
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/* Handling the offload flags (olflags) field takes computation
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* time when receiving packets. Therefore we provide a flag to disable
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* the processing of the olflags field when they are not needed. This
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* gives improved performance, at the cost of losing the offload info
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* in the received packet
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*/
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#ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
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/* Vlan present flag shift */
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#define VP_SHIFT (2)
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/* L3 type shift */
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#define L3TYPE_SHIFT (4)
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/* L4 type shift */
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#define L4TYPE_SHIFT (7)
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/* HBO flag shift */
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#define HBOFLAG_SHIFT (10)
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/* RXE flag shift */
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#define RXEFLAG_SHIFT (13)
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/* IPE/L4E flag shift */
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#define L3L4EFLAG_SHIFT (14)
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/* shift PKT_RX_L4_CKSUM_GOOD into one byte by 1 bit */
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#define CKSUM_SHIFT (1)
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static inline void
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fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
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{
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__m128i ptype0, ptype1, vtag0, vtag1, eflag0, eflag1, cksumflag;
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union {
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uint16_t e[4];
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uint64_t dword;
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} vol;
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const __m128i pkttype_msk = _mm_set_epi16(
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0x0000, 0x0000, 0x0000, 0x0000,
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PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
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PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
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PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
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PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
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/* mask everything except rss type */
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const __m128i rsstype_msk = _mm_set_epi16(
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0x0000, 0x0000, 0x0000, 0x0000,
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0x000F, 0x000F, 0x000F, 0x000F);
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/* mask for HBO and RXE flag flags */
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const __m128i rxe_msk = _mm_set_epi16(
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0x0000, 0x0000, 0x0000, 0x0000,
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0x0001, 0x0001, 0x0001, 0x0001);
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/* mask the lower byte of ol_flags */
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const __m128i ol_flags_msk = _mm_set_epi16(
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0x0000, 0x0000, 0x0000, 0x0000,
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0x00FF, 0x00FF, 0x00FF, 0x00FF);
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const __m128i l3l4cksum_flag = _mm_set_epi8(0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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(PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
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(PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT,
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(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
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(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT);
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const __m128i rxe_flag = _mm_set_epi8(0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0);
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/* map rss type to rss hash flag */
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const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
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0, 0, 0, PKT_RX_RSS_HASH,
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PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
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PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
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/* Calculate RSS_hash and Vlan fields */
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ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
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ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
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vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
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vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
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ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
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ptype0 = _mm_and_si128(ptype0, rsstype_msk);
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ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
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vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
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eflag0 = vtag1;
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cksumflag = vtag1;
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vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
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vtag1 = _mm_and_si128(vtag1, pkttype_msk);
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vtag1 = _mm_or_si128(ptype0, vtag1);
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/* Process err flags, simply set RECIP_ERR bit if HBO/IXE is set */
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eflag1 = _mm_srli_epi16(eflag0, RXEFLAG_SHIFT);
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eflag0 = _mm_srli_epi16(eflag0, HBOFLAG_SHIFT);
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eflag0 = _mm_or_si128(eflag0, eflag1);
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eflag0 = _mm_and_si128(eflag0, rxe_msk);
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eflag0 = _mm_shuffle_epi8(rxe_flag, eflag0);
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vtag1 = _mm_or_si128(eflag0, vtag1);
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/* Process L4/L3 checksum error flags */
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cksumflag = _mm_srli_epi16(cksumflag, L3L4EFLAG_SHIFT);
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cksumflag = _mm_shuffle_epi8(l3l4cksum_flag, cksumflag);
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/* clean the higher byte and shift back the flag bits */
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cksumflag = _mm_and_si128(cksumflag, ol_flags_msk);
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cksumflag = _mm_slli_epi16(cksumflag, CKSUM_SHIFT);
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vtag1 = _mm_or_si128(cksumflag, vtag1);
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vol.dword = _mm_cvtsi128_si64(vtag1);
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rx_pkts[0]->ol_flags = vol.e[0];
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rx_pkts[1]->ol_flags = vol.e[1];
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rx_pkts[2]->ol_flags = vol.e[2];
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rx_pkts[3]->ol_flags = vol.e[3];
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}
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/* @note: When this function is changed, make corresponding change to
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* fm10k_dev_supported_ptypes_get().
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*/
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static inline void
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fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
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{
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__m128i l3l4type0, l3l4type1, l3type, l4type;
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union {
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uint16_t e[4];
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uint64_t dword;
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} vol;
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/* L3 pkt type mask Bit4 to Bit6 */
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const __m128i l3type_msk = _mm_set_epi16(
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0x0000, 0x0000, 0x0000, 0x0000,
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0x0070, 0x0070, 0x0070, 0x0070);
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/* L4 pkt type mask Bit7 to Bit9 */
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const __m128i l4type_msk = _mm_set_epi16(
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0x0000, 0x0000, 0x0000, 0x0000,
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0x0380, 0x0380, 0x0380, 0x0380);
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/* convert RRC l3 type to mbuf format */
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const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
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RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
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RTE_PTYPE_L3_IPV4, 0);
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/* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
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* to fill into8 bits length.
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*/
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const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
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RTE_PTYPE_TUNNEL_GENEVE >> 8,
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RTE_PTYPE_TUNNEL_NVGRE >> 8,
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RTE_PTYPE_TUNNEL_VXLAN >> 8,
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RTE_PTYPE_TUNNEL_GRE >> 8,
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RTE_PTYPE_L4_UDP >> 8,
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RTE_PTYPE_L4_TCP >> 8,
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0);
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l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
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l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
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l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
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l3type = _mm_and_si128(l3l4type0, l3type_msk);
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l4type = _mm_and_si128(l3l4type0, l4type_msk);
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l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
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l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
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l3type = _mm_shuffle_epi8(l3type_flags, l3type);
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/* l4type_flags shift-left for 8 bits, need shift-right back */
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l4type = _mm_shuffle_epi8(l4type_flags, l4type);
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l4type = _mm_slli_epi16(l4type, 8);
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l3l4type0 = _mm_or_si128(l3type, l4type);
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vol.dword = _mm_cvtsi128_si64(l3l4type0);
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rx_pkts[0]->packet_type = vol.e[0];
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rx_pkts[1]->packet_type = vol.e[1];
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rx_pkts[2]->packet_type = vol.e[2];
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rx_pkts[3]->packet_type = vol.e[3];
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}
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#else
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#define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
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#define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
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#endif
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int __rte_cold
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fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
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{
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#ifndef RTE_LIBRTE_IEEE1588
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struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
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struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
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#ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
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/* whithout rx ol_flags, no VP flag report */
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if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
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return -1;
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#endif
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/* no fdir support */
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if (fconf->mode != RTE_FDIR_MODE_NONE)
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return -1;
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/* no header split support */
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if (rxmode->offloads & DEV_RX_OFFLOAD_HEADER_SPLIT)
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return -1;
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return 0;
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#else
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RTE_SET_USED(dev);
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return -1;
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#endif
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}
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int __rte_cold
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fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
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{
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uintptr_t p;
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struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
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mb_def.nb_segs = 1;
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/* data_off will be ajusted after new mbuf allocated for 512-byte
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* alignment.
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*/
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mb_def.data_off = RTE_PKTMBUF_HEADROOM;
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mb_def.port = rxq->port_id;
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rte_mbuf_refcnt_set(&mb_def, 1);
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/* prevent compiler reordering: rearm_data covers previous fields */
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rte_compiler_barrier();
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p = (uintptr_t)&mb_def.rearm_data;
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rxq->mbuf_initializer = *(uint64_t *)p;
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return 0;
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}
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static inline void
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fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
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{
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int i;
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uint16_t rx_id;
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volatile union fm10k_rx_desc *rxdp;
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struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
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struct rte_mbuf *mb0, *mb1;
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__m128i head_off = _mm_set_epi64x(
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RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
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RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
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__m128i dma_addr0, dma_addr1;
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/* Rx buffer need to be aligned with 512 byte */
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const __m128i hba_msk = _mm_set_epi64x(0,
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UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
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rxdp = rxq->hw_ring + rxq->rxrearm_start;
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/* Pull 'n' more MBUFs into the software ring */
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if (rte_mempool_get_bulk(rxq->mp,
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(void *)mb_alloc,
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RTE_FM10K_RXQ_REARM_THRESH) < 0) {
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dma_addr0 = _mm_setzero_si128();
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/* Clean up all the HW/SW ring content */
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for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
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mb_alloc[i] = &rxq->fake_mbuf;
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_mm_store_si128((__m128i *)&rxdp[i].q,
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dma_addr0);
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}
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rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
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RTE_FM10K_RXQ_REARM_THRESH;
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return;
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}
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/* Initialize the mbufs in vector, process 2 mbufs in one loop */
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for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
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__m128i vaddr0, vaddr1;
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uintptr_t p0, p1;
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mb0 = mb_alloc[0];
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mb1 = mb_alloc[1];
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/* Flush mbuf with pkt template.
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* Data to be rearmed is 6 bytes long.
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*/
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p0 = (uintptr_t)&mb0->rearm_data;
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*(uint64_t *)p0 = rxq->mbuf_initializer;
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p1 = (uintptr_t)&mb1->rearm_data;
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*(uint64_t *)p1 = rxq->mbuf_initializer;
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/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
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RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
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offsetof(struct rte_mbuf, buf_addr) + 8);
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vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
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vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
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/* convert pa to dma_addr hdr/data */
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dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
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dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
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/* add headroom to pa values */
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dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
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dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
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/* Do 512 byte alignment to satisfy HW requirement, in the
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* meanwhile, set Header Buffer Address to zero.
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*/
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dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
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dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
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/* flush desc with pa dma_addr */
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_mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
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_mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
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/* enforce 512B alignment on default Rx virtual addresses */
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mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
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+ RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
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- (char *)mb0->buf_addr);
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mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
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+ RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
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- (char *)mb1->buf_addr);
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}
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rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
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if (rxq->rxrearm_start >= rxq->nb_desc)
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rxq->rxrearm_start = 0;
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rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
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rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
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(rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
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/* Update the tail pointer on the NIC */
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FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
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}
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void __rte_cold
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fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
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{
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const unsigned mask = rxq->nb_desc - 1;
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unsigned i;
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if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
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return;
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/* free all mbufs that are valid in the ring */
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if (rxq->rxrearm_nb == 0) {
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for (i = 0; i < rxq->nb_desc; i++)
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if (rxq->sw_ring[i] != NULL)
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rte_pktmbuf_free_seg(rxq->sw_ring[i]);
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} else {
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for (i = rxq->next_dd; i != rxq->rxrearm_start;
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i = (i + 1) & mask)
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rte_pktmbuf_free_seg(rxq->sw_ring[i]);
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}
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rxq->rxrearm_nb = rxq->nb_desc;
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/* set all entries to NULL */
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memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
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}
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static inline uint16_t
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fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts, uint8_t *split_packet)
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{
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volatile union fm10k_rx_desc *rxdp;
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struct rte_mbuf **mbufp;
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uint16_t nb_pkts_recd;
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int pos;
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struct fm10k_rx_queue *rxq = rx_queue;
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uint64_t var;
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__m128i shuf_msk;
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__m128i dd_check, eop_check;
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uint16_t next_dd;
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next_dd = rxq->next_dd;
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/* Just the act of getting into the function from the application is
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* going to cost about 7 cycles
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*/
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rxdp = rxq->hw_ring + next_dd;
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rte_prefetch0(rxdp);
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/* See if we need to rearm the RX queue - gives the prefetch a bit
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* of time to act
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*/
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if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
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fm10k_rxq_rearm(rxq);
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/* Before we start moving massive data around, check to see if
|
|
* there is actually a packet available
|
|
*/
|
|
if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
|
|
return 0;
|
|
|
|
/* Vecotr RX will process 4 packets at a time, strip the unaligned
|
|
* tails in case it's not multiple of 4.
|
|
*/
|
|
nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
|
|
|
|
/* 4 packets DD mask */
|
|
dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
|
|
|
|
/* 4 packets EOP mask */
|
|
eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
|
|
|
|
/* mask to shuffle from desc. to mbuf */
|
|
shuf_msk = _mm_set_epi8(
|
|
7, 6, 5, 4, /* octet 4~7, 32bits rss */
|
|
15, 14, /* octet 14~15, low 16 bits vlan_macip */
|
|
13, 12, /* octet 12~13, 16 bits data_len */
|
|
0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
|
|
13, 12, /* octet 12~13, low 16 bits pkt_len */
|
|
0xFF, 0xFF, /* skip high 16 bits pkt_type */
|
|
0xFF, 0xFF /* Skip pkt_type field in shuffle operation */
|
|
);
|
|
/*
|
|
* Compile-time verify the shuffle mask
|
|
* NOTE: some field positions already verified above, but duplicated
|
|
* here for completeness in case of future modifications.
|
|
*/
|
|
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
|
|
offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
|
|
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
|
|
offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
|
|
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
|
|
offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
|
|
RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
|
|
offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
|
|
|
|
/* Cache is empty -> need to scan the buffer rings, but first move
|
|
* the next 'n' mbufs into the cache
|
|
*/
|
|
mbufp = &rxq->sw_ring[next_dd];
|
|
|
|
/* A. load 4 packet in one loop
|
|
* [A*. mask out 4 unused dirty field in desc]
|
|
* B. copy 4 mbuf point from swring to rx_pkts
|
|
* C. calc the number of DD bits among the 4 packets
|
|
* [C*. extract the end-of-packet bit, if requested]
|
|
* D. fill info. from desc to mbuf
|
|
*/
|
|
for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
|
|
pos += RTE_FM10K_DESCS_PER_LOOP,
|
|
rxdp += RTE_FM10K_DESCS_PER_LOOP) {
|
|
__m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
|
|
__m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
|
|
__m128i zero, staterr, sterr_tmp1, sterr_tmp2;
|
|
__m128i mbp1;
|
|
/* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
|
|
#if defined(RTE_ARCH_X86_64)
|
|
__m128i mbp2;
|
|
#endif
|
|
|
|
/* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
|
|
mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
|
|
|
|
/* Read desc statuses backwards to avoid race condition */
|
|
/* A.1 load 4 pkts desc */
|
|
descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
|
|
rte_compiler_barrier();
|
|
|
|
/* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
|
|
_mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
|
|
|
|
#if defined(RTE_ARCH_X86_64)
|
|
/* B.1 load 2 64 bit mbuf poitns */
|
|
mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
|
|
#endif
|
|
|
|
descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
|
|
rte_compiler_barrier();
|
|
/* B.1 load 2 mbuf point */
|
|
descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
|
|
rte_compiler_barrier();
|
|
descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
|
|
|
|
#if defined(RTE_ARCH_X86_64)
|
|
/* B.2 copy 2 mbuf point into rx_pkts */
|
|
_mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
|
|
#endif
|
|
|
|
/* avoid compiler reorder optimization */
|
|
rte_compiler_barrier();
|
|
|
|
if (split_packet) {
|
|
rte_mbuf_prefetch_part2(rx_pkts[pos]);
|
|
rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
|
|
rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
|
|
rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
|
|
}
|
|
|
|
/* D.1 pkt 3,4 convert format from desc to pktmbuf */
|
|
pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
|
|
pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
|
|
|
|
/* C.1 4=>2 filter staterr info only */
|
|
sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
|
|
/* C.1 4=>2 filter staterr info only */
|
|
sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
|
|
|
|
/* set ol_flags with vlan packet type */
|
|
fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
|
|
|
|
/* D.1 pkt 1,2 convert format from desc to pktmbuf */
|
|
pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
|
|
pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
|
|
|
|
/* C.2 get 4 pkts staterr value */
|
|
zero = _mm_xor_si128(dd_check, dd_check);
|
|
staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
|
|
|
|
/* D.3 copy final 3,4 data to rx_pkts */
|
|
_mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
|
|
pkt_mb4);
|
|
_mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
|
|
pkt_mb3);
|
|
|
|
/* C* extract and record EOP bit */
|
|
if (split_packet) {
|
|
__m128i eop_shuf_mask = _mm_set_epi8(
|
|
0xFF, 0xFF, 0xFF, 0xFF,
|
|
0xFF, 0xFF, 0xFF, 0xFF,
|
|
0xFF, 0xFF, 0xFF, 0xFF,
|
|
0x04, 0x0C, 0x00, 0x08
|
|
);
|
|
|
|
/* and with mask to extract bits, flipping 1-0 */
|
|
__m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
|
|
/* the staterr values are not in order, as the count
|
|
* count of dd bits doesn't care. However, for end of
|
|
* packet tracking, we do care, so shuffle. This also
|
|
* compresses the 32-bit values to 8-bit
|
|
*/
|
|
eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
|
|
/* store the resulting 32-bit value */
|
|
*(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
|
|
split_packet += RTE_FM10K_DESCS_PER_LOOP;
|
|
|
|
/* zero-out next pointers */
|
|
rx_pkts[pos]->next = NULL;
|
|
rx_pkts[pos + 1]->next = NULL;
|
|
rx_pkts[pos + 2]->next = NULL;
|
|
rx_pkts[pos + 3]->next = NULL;
|
|
}
|
|
|
|
/* C.3 calc available number of desc */
|
|
staterr = _mm_and_si128(staterr, dd_check);
|
|
staterr = _mm_packs_epi32(staterr, zero);
|
|
|
|
/* D.3 copy final 1,2 data to rx_pkts */
|
|
_mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
|
|
pkt_mb2);
|
|
_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
|
|
pkt_mb1);
|
|
|
|
fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
|
|
|
|
/* C.4 calc avaialbe number of desc */
|
|
var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
|
|
nb_pkts_recd += var;
|
|
if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
|
|
break;
|
|
}
|
|
|
|
/* Update our internal tail pointer */
|
|
rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
|
|
rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
|
|
rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
|
|
|
|
return nb_pkts_recd;
|
|
}
|
|
|
|
/* vPMD receive routine
|
|
*
|
|
* Notice:
|
|
* - don't support ol_flags for rss and csum err
|
|
*/
|
|
uint16_t
|
|
fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
|
|
}
|
|
|
|
static inline uint16_t
|
|
fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
|
|
struct rte_mbuf **rx_bufs,
|
|
uint16_t nb_bufs, uint8_t *split_flags)
|
|
{
|
|
struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
|
|
struct rte_mbuf *start = rxq->pkt_first_seg;
|
|
struct rte_mbuf *end = rxq->pkt_last_seg;
|
|
unsigned pkt_idx, buf_idx;
|
|
|
|
for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
|
|
if (end != NULL) {
|
|
/* processing a split packet */
|
|
end->next = rx_bufs[buf_idx];
|
|
start->nb_segs++;
|
|
start->pkt_len += rx_bufs[buf_idx]->data_len;
|
|
end = end->next;
|
|
|
|
if (!split_flags[buf_idx]) {
|
|
/* it's the last packet of the set */
|
|
#ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
|
|
start->hash = end->hash;
|
|
start->ol_flags = end->ol_flags;
|
|
start->packet_type = end->packet_type;
|
|
#endif
|
|
pkts[pkt_idx++] = start;
|
|
start = end = NULL;
|
|
}
|
|
} else {
|
|
/* not processing a split packet */
|
|
if (!split_flags[buf_idx]) {
|
|
/* not a split packet, save and skip */
|
|
pkts[pkt_idx++] = rx_bufs[buf_idx];
|
|
continue;
|
|
}
|
|
end = start = rx_bufs[buf_idx];
|
|
}
|
|
}
|
|
|
|
/* save the partial packet for next time */
|
|
rxq->pkt_first_seg = start;
|
|
rxq->pkt_last_seg = end;
|
|
memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
|
|
return pkt_idx;
|
|
}
|
|
|
|
/*
|
|
* vPMD receive routine that reassembles scattered packets
|
|
*
|
|
* Notice:
|
|
* - don't support ol_flags for rss and csum err
|
|
* - nb_pkts > RTE_FM10K_MAX_RX_BURST, only scan RTE_FM10K_MAX_RX_BURST
|
|
* numbers of DD bit
|
|
*/
|
|
uint16_t
|
|
fm10k_recv_scattered_pkts_vec(void *rx_queue,
|
|
struct rte_mbuf **rx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
struct fm10k_rx_queue *rxq = rx_queue;
|
|
uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
|
|
unsigned i = 0;
|
|
|
|
/* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
|
|
nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
|
|
/* get some new buffers */
|
|
uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
|
|
split_flags);
|
|
if (nb_bufs == 0)
|
|
return 0;
|
|
|
|
/* happy day case, full burst + no packets to be joined */
|
|
const uint64_t *split_fl64 = (uint64_t *)split_flags;
|
|
|
|
if (rxq->pkt_first_seg == NULL &&
|
|
split_fl64[0] == 0 && split_fl64[1] == 0 &&
|
|
split_fl64[2] == 0 && split_fl64[3] == 0)
|
|
return nb_bufs;
|
|
|
|
/* reassemble any packets that need reassembly*/
|
|
if (rxq->pkt_first_seg == NULL) {
|
|
/* find the first split flag, and only reassemble then*/
|
|
while (i < nb_bufs && !split_flags[i])
|
|
i++;
|
|
if (i == nb_bufs)
|
|
return nb_bufs;
|
|
rxq->pkt_first_seg = rx_pkts[i];
|
|
}
|
|
return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
|
|
&split_flags[i]);
|
|
}
|
|
|
|
static const struct fm10k_txq_ops vec_txq_ops = {
|
|
.reset = fm10k_reset_tx_queue,
|
|
};
|
|
|
|
void __rte_cold
|
|
fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
|
|
{
|
|
txq->ops = &vec_txq_ops;
|
|
}
|
|
|
|
int __rte_cold
|
|
fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq)
|
|
{
|
|
/* Vector TX can't offload any features yet */
|
|
if (txq->offloads != 0)
|
|
return -1;
|
|
|
|
if (txq->tx_ftag_en)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void
|
|
vtx1(volatile struct fm10k_tx_desc *txdp,
|
|
struct rte_mbuf *pkt, uint64_t flags)
|
|
{
|
|
__m128i descriptor = _mm_set_epi64x(flags << 56 |
|
|
(uint64_t)pkt->vlan_tci << 16 | (uint64_t)pkt->data_len,
|
|
MBUF_DMA_ADDR(pkt));
|
|
_mm_store_si128((__m128i *)txdp, descriptor);
|
|
}
|
|
|
|
static inline void
|
|
vtx(volatile struct fm10k_tx_desc *txdp,
|
|
struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
|
|
vtx1(txdp, *pkt, flags);
|
|
}
|
|
|
|
static __rte_always_inline int
|
|
fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
|
|
{
|
|
struct rte_mbuf **txep;
|
|
uint8_t flags;
|
|
uint32_t n;
|
|
uint32_t i;
|
|
int nb_free = 0;
|
|
struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
|
|
|
|
/* check DD bit on threshold descriptor */
|
|
flags = txq->hw_ring[txq->next_dd].flags;
|
|
if (!(flags & FM10K_TXD_FLAG_DONE))
|
|
return 0;
|
|
|
|
n = txq->rs_thresh;
|
|
|
|
/* First buffer to free from S/W ring is at index
|
|
* next_dd - (rs_thresh-1)
|
|
*/
|
|
txep = &txq->sw_ring[txq->next_dd - (n - 1)];
|
|
m = rte_pktmbuf_prefree_seg(txep[0]);
|
|
if (likely(m != NULL)) {
|
|
free[0] = m;
|
|
nb_free = 1;
|
|
for (i = 1; i < n; i++) {
|
|
m = rte_pktmbuf_prefree_seg(txep[i]);
|
|
if (likely(m != NULL)) {
|
|
if (likely(m->pool == free[0]->pool))
|
|
free[nb_free++] = m;
|
|
else {
|
|
rte_mempool_put_bulk(free[0]->pool,
|
|
(void *)free, nb_free);
|
|
free[0] = m;
|
|
nb_free = 1;
|
|
}
|
|
}
|
|
}
|
|
rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
|
|
} else {
|
|
for (i = 1; i < n; i++) {
|
|
m = rte_pktmbuf_prefree_seg(txep[i]);
|
|
if (m != NULL)
|
|
rte_mempool_put(m->pool, m);
|
|
}
|
|
}
|
|
|
|
/* buffers were freed, update counters */
|
|
txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
|
|
txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
|
|
if (txq->next_dd >= txq->nb_desc)
|
|
txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
|
|
|
|
return txq->rs_thresh;
|
|
}
|
|
|
|
static __rte_always_inline void
|
|
tx_backlog_entry(struct rte_mbuf **txep,
|
|
struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < (int)nb_pkts; ++i)
|
|
txep[i] = tx_pkts[i];
|
|
}
|
|
|
|
uint16_t
|
|
fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
|
|
uint16_t nb_pkts)
|
|
{
|
|
struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
|
|
volatile struct fm10k_tx_desc *txdp;
|
|
struct rte_mbuf **txep;
|
|
uint16_t n, nb_commit, tx_id;
|
|
uint64_t flags = FM10K_TXD_FLAG_LAST;
|
|
uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
|
|
int i;
|
|
|
|
/* cross rx_thresh boundary is not allowed */
|
|
nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
|
|
|
|
if (txq->nb_free < txq->free_thresh)
|
|
fm10k_tx_free_bufs(txq);
|
|
|
|
nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
|
|
if (unlikely(nb_pkts == 0))
|
|
return 0;
|
|
|
|
tx_id = txq->next_free;
|
|
txdp = &txq->hw_ring[tx_id];
|
|
txep = &txq->sw_ring[tx_id];
|
|
|
|
txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
|
|
|
|
n = (uint16_t)(txq->nb_desc - tx_id);
|
|
if (nb_commit >= n) {
|
|
tx_backlog_entry(txep, tx_pkts, n);
|
|
|
|
for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
|
|
vtx1(txdp, *tx_pkts, flags);
|
|
|
|
vtx1(txdp, *tx_pkts++, rs);
|
|
|
|
nb_commit = (uint16_t)(nb_commit - n);
|
|
|
|
tx_id = 0;
|
|
txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
|
|
|
|
/* avoid reach the end of ring */
|
|
txdp = &(txq->hw_ring[tx_id]);
|
|
txep = &txq->sw_ring[tx_id];
|
|
}
|
|
|
|
tx_backlog_entry(txep, tx_pkts, nb_commit);
|
|
|
|
vtx(txdp, tx_pkts, nb_commit, flags);
|
|
|
|
tx_id = (uint16_t)(tx_id + nb_commit);
|
|
if (tx_id > txq->next_rs) {
|
|
txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
|
|
txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
|
|
}
|
|
|
|
txq->next_free = tx_id;
|
|
|
|
FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
|
|
|
|
return nb_pkts;
|
|
}
|
|
|
|
static void __rte_cold
|
|
fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
|
|
{
|
|
static const struct fm10k_tx_desc zeroed_desc = {0};
|
|
struct rte_mbuf **txe = txq->sw_ring;
|
|
uint16_t i;
|
|
|
|
/* Zero out HW ring memory */
|
|
for (i = 0; i < txq->nb_desc; i++)
|
|
txq->hw_ring[i] = zeroed_desc;
|
|
|
|
/* Initialize SW ring entries */
|
|
for (i = 0; i < txq->nb_desc; i++)
|
|
txe[i] = NULL;
|
|
|
|
txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
|
|
txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
|
|
|
|
txq->next_free = 0;
|
|
txq->nb_used = 0;
|
|
/* Always allow 1 descriptor to be un-allocated to avoid
|
|
* a H/W race condition
|
|
*/
|
|
txq->nb_free = (uint16_t)(txq->nb_desc - 1);
|
|
FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);
|
|
}
|