9c99878aa1
Introduce the RTE_LOG_REGISTER macro to avoid the code duplication in the logtype registration process. It is a wrapper macro for declaring the logtype, registering it and setting its level in the constructor context. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com> Acked-by: Sachin Saxena <sachin.saxena@nxp.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
589 lines
15 KiB
C
589 lines
15 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation
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*/
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#include <stdint.h>
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#include <rte_bus_pci.h>
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#include <rte_ethdev.h>
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#include <rte_pci.h>
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#include <rte_malloc.h>
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#include <rte_mbuf.h>
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#include <rte_sched.h>
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#include <rte_ethdev_driver.h>
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#include <rte_io.h>
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#include <rte_rawdev.h>
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#include <rte_rawdev_pmd.h>
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#include <rte_bus_ifpga.h>
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#include <ifpga_common.h>
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#include <ifpga_logs.h>
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#include <ifpga_rawdev.h>
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#include "ipn3ke_rawdev_api.h"
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#include "ipn3ke_flow.h"
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#include "ipn3ke_logs.h"
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#include "ipn3ke_ethdev.h"
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static const struct rte_afu_uuid afu_uuid_ipn3ke_map[] = {
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{ MAP_UUID_10G_LOW, MAP_UUID_10G_HIGH },
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{ IPN3KE_UUID_10G_LOW, IPN3KE_UUID_10G_HIGH },
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{ IPN3KE_UUID_VBNG_LOW, IPN3KE_UUID_VBNG_HIGH},
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{ IPN3KE_UUID_25G_LOW, IPN3KE_UUID_25G_HIGH },
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{ 0, 0 /* sentinel */ },
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};
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struct ipn3ke_pub_func ipn3ke_bridge_func;
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static int
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ipn3ke_indirect_read(struct ipn3ke_hw *hw, uint32_t *rd_data,
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uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel)
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{
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uint32_t i, try_cnt;
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uint64_t indirect_value;
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volatile void *indirect_addrs;
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uint64_t target_addr;
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uint64_t read_data = 0;
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if (eth_group_sel != 0 && eth_group_sel != 1)
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return -1;
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target_addr = addr | dev_sel << 17;
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indirect_value = RCMD | target_addr << 32;
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indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10;
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rte_delay_us(10);
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rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
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i = 0;
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try_cnt = 10;
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indirect_addrs = hw->eth_group_bar[eth_group_sel] +
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0x18;
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do {
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read_data = rte_read64(indirect_addrs);
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if ((read_data >> 32) == 1)
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break;
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i++;
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} while (i <= try_cnt);
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if (i > try_cnt)
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return -1;
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*rd_data = rte_le_to_cpu_32(read_data);
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return 0;
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}
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static int
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ipn3ke_indirect_write(struct ipn3ke_hw *hw, uint32_t wr_data,
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uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel)
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{
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volatile void *indirect_addrs;
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uint64_t indirect_value;
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uint64_t target_addr;
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if (eth_group_sel != 0 && eth_group_sel != 1)
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return -1;
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target_addr = addr | dev_sel << 17;
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indirect_value = WCMD | target_addr << 32 | wr_data;
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indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10;
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rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
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return 0;
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}
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static int
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ipn3ke_indirect_mac_read(struct ipn3ke_hw *hw, uint32_t *rd_data,
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uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel)
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{
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uint32_t dev_sel;
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if (mac_num >= hw->port_num)
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return -1;
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mac_num &= 0x7;
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dev_sel = mac_num * 2 + 3;
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return ipn3ke_indirect_read(hw, rd_data, addr, dev_sel, eth_group_sel);
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}
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static int
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ipn3ke_indirect_mac_write(struct ipn3ke_hw *hw, uint32_t wr_data,
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uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel)
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{
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uint32_t dev_sel;
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if (mac_num >= hw->port_num)
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return -1;
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mac_num &= 0x7;
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dev_sel = mac_num * 2 + 3;
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return ipn3ke_indirect_write(hw, wr_data, addr, dev_sel, eth_group_sel);
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}
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static void
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ipn3ke_hw_cap_init(struct ipn3ke_hw *hw)
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{
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hw->hw_cap.version_number = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0), 0, 0xFFFF);
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hw->hw_cap.capability_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x8), 0, 0xFFFFFFFF);
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hw->hw_cap.status_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x10), 0, 0xFFFFFFFF);
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hw->hw_cap.control_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x18), 0, 0xFFFFFFFF);
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hw->hw_cap.classify_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x20), 0, 0xFFFFFFFF);
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hw->hw_cap.classy_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x24), 0, 0xFFFF);
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hw->hw_cap.policer_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x28), 0, 0xFFFFFFFF);
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hw->hw_cap.policer_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x2C), 0, 0xFFFF);
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hw->hw_cap.rss_key_array_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x30), 0, 0xFFFFFFFF);
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hw->hw_cap.rss_key_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x34), 0, 0xFFFF);
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hw->hw_cap.rss_indirection_table_array_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x38), 0, 0xFFFFFFFF);
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hw->hw_cap.rss_indirection_table_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x3C), 0, 0xFFFF);
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hw->hw_cap.dmac_map_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x40), 0, 0xFFFFFFFF);
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hw->hw_cap.dmac_map_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x44), 0, 0xFFFF);
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hw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x48), 0, 0xFFFFFFFF);
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hw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x4C), 0, 0xFFFF);
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hw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x50), 0, 0xFFFFFFFF);
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hw->hw_cap.ccb_entry_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x54), 0, 0xFFFF);
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hw->hw_cap.qos_offset = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x58), 0, 0xFFFFFFFF);
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hw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw,
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(IPN3KE_HW_BASE + 0x5C), 0, 0xFFFF);
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hw->hw_cap.num_rx_flow = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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0, 0xFFFF);
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hw->hw_cap.num_rss_blocks = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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4, 0xFFFF);
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hw->hw_cap.num_dmac_map = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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8, 0xFFFF);
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hw->hw_cap.num_tx_flow = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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0xC, 0xFFFF);
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hw->hw_cap.num_smac_map = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
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0x10, 0xFFFF);
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hw->hw_cap.link_speed_mbps = IPN3KE_MASK_READ_REG(hw,
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IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET,
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0, 0xFFFFF);
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}
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static int
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ipn3ke_vbng_init_done(struct ipn3ke_hw *hw)
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{
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uint32_t timeout = 10000;
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while (timeout > 0) {
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if (IPN3KE_READ_REG(hw, IPN3KE_VBNG_INIT_STS)
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== IPN3KE_VBNG_INIT_DONE)
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break;
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rte_delay_us(1000);
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timeout--;
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}
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if (!timeout) {
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IPN3KE_AFU_PMD_ERR("IPN3KE vBNG INIT timeout.\n");
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return -1;
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}
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return 0;
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}
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static uint32_t
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ipn3ke_mtu_cal(uint32_t tx, uint32_t rx)
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{
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uint32_t tmp;
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tmp = RTE_MIN(tx, rx);
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tmp = RTE_MAX(tmp, (uint32_t)RTE_ETHER_MIN_MTU);
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tmp = RTE_MIN(tmp, (uint32_t)(IPN3KE_MAC_FRAME_SIZE_MAX -
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IPN3KE_ETH_OVERHEAD));
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return tmp;
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}
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static void
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ipn3ke_mtu_set(struct ipn3ke_hw *hw, uint32_t mac_num,
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uint32_t eth_group_sel, uint32_t txaddr, uint32_t rxaddr)
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{
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uint32_t tx;
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uint32_t rx;
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uint32_t tmp;
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if (!(*hw->f_mac_read) || !(*hw->f_mac_write))
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return;
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(*hw->f_mac_read)(hw,
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&tx,
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txaddr,
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mac_num,
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eth_group_sel);
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(*hw->f_mac_read)(hw,
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&rx,
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rxaddr,
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mac_num,
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eth_group_sel);
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tmp = ipn3ke_mtu_cal(tx, rx);
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(*hw->f_mac_write)(hw,
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tmp,
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txaddr,
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mac_num,
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eth_group_sel);
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(*hw->f_mac_write)(hw,
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tmp,
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rxaddr,
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mac_num,
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eth_group_sel);
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}
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static void
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ipn3ke_10G_mtu_setup(struct ipn3ke_hw *hw, uint32_t mac_num,
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uint32_t eth_group_sel)
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{
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ipn3ke_mtu_set(hw, mac_num, eth_group_sel,
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IPN3KE_10G_TX_FRAME_MAXLENGTH, IPN3KE_10G_RX_FRAME_MAXLENGTH);
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}
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static void
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ipn3ke_25G_mtu_setup(struct ipn3ke_hw *hw, uint32_t mac_num,
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uint32_t eth_group_sel)
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{
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ipn3ke_mtu_set(hw, mac_num, eth_group_sel,
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IPN3KE_25G_MAX_TX_SIZE_CONFIG, IPN3KE_25G_MAX_RX_SIZE_CONFIG);
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}
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static void
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ipn3ke_mtu_setup(struct ipn3ke_hw *hw)
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{
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int i;
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if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
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for (i = 0; i < hw->port_num; i++) {
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ipn3ke_10G_mtu_setup(hw, i, 0);
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ipn3ke_10G_mtu_setup(hw, i, 1);
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}
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} else if (hw->retimer.mac_type ==
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IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
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for (i = 0; i < hw->port_num; i++) {
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ipn3ke_25G_mtu_setup(hw, i, 0);
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ipn3ke_25G_mtu_setup(hw, i, 1);
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}
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}
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}
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static int
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ipn3ke_hw_init(struct rte_afu_device *afu_dev,
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struct ipn3ke_hw *hw)
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{
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struct rte_rawdev *rawdev;
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int ret;
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int i;
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uint64_t port_num, mac_type, index;
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rawdev = afu_dev->rawdev;
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hw->afu_id.uuid.uuid_low = afu_dev->id.uuid.uuid_low;
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hw->afu_id.uuid.uuid_high = afu_dev->id.uuid.uuid_high;
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hw->afu_id.port = afu_dev->id.port;
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hw->hw_addr = (uint8_t *)(afu_dev->mem_resource[0].addr);
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hw->f_mac_read = ipn3ke_indirect_mac_read;
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hw->f_mac_write = ipn3ke_indirect_mac_write;
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hw->rawdev = rawdev;
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rawdev->dev_ops->attr_get(rawdev,
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"LineSideBARIndex", &index);
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hw->eth_group_bar[0] = (uint8_t *)(afu_dev->mem_resource[index].addr);
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rawdev->dev_ops->attr_get(rawdev,
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"NICSideBARIndex", &index);
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hw->eth_group_bar[1] = (uint8_t *)(afu_dev->mem_resource[index].addr);
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rawdev->dev_ops->attr_get(rawdev,
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"LineSideLinkPortNum", &port_num);
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hw->retimer.port_num = (int)port_num;
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hw->port_num = hw->retimer.port_num;
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rawdev->dev_ops->attr_get(rawdev,
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"LineSideMACType", &mac_type);
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hw->retimer.mac_type = (int)mac_type;
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hw->acc_tm = 0;
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hw->acc_flow = 0;
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if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
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afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
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/* After power on, wait until init done */
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if (ipn3ke_vbng_init_done(hw))
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return -1;
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ipn3ke_hw_cap_init(hw);
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/* Reset vBNG IP */
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IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);
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rte_delay_us(10);
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IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);
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/* After reset, wait until init done */
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if (ipn3ke_vbng_init_done(hw))
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return -1;
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hw->acc_tm = 1;
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hw->acc_flow = 1;
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IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n",
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IPN3KE_READ_REG(hw, 0));
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}
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if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
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/* Enable inter connect channel */
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for (i = 0; i < hw->port_num; i++) {
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/* Enable the TX path */
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ipn3ke_xmac_tx_enable(hw, i, 1);
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/* Disables source address override */
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ipn3ke_xmac_smac_ovd_dis(hw, i, 1);
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/* Enable the RX path */
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ipn3ke_xmac_rx_enable(hw, i, 1);
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
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/* Clear line RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
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}
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} else if (hw->retimer.mac_type ==
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IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
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/* Enable inter connect channel */
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for (i = 0; i < hw->port_num; i++) {
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
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/* Clear line side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
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}
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}
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/* init mtu */
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ipn3ke_mtu_setup(hw);
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ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);
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if (ret)
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IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d",
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ret);
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hw->tm_hw_enable = 0;
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hw->flow_hw_enable = 0;
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if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
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afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
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ret = ipn3ke_hw_tm_init(hw);
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if (ret)
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return ret;
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hw->tm_hw_enable = 1;
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ret = ipn3ke_flow_init(hw);
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if (ret)
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return ret;
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hw->flow_hw_enable = 1;
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}
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return 0;
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}
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static void
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ipn3ke_hw_uninit(struct ipn3ke_hw *hw)
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{
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int i;
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if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
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for (i = 0; i < hw->port_num; i++) {
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/* Disable the TX path */
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ipn3ke_xmac_tx_disable(hw, i, 1);
|
|
|
|
/* Disable the RX path */
|
|
ipn3ke_xmac_rx_disable(hw, i, 1);
|
|
|
|
/* Clear NIC side TX statistics counters */
|
|
ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
|
|
|
|
/* Clear NIC side RX statistics counters */
|
|
ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
|
|
|
|
/* Clear line side TX statistics counters */
|
|
ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
|
|
|
|
/* Clear line side RX statistics counters */
|
|
ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
|
|
}
|
|
} else if (hw->retimer.mac_type ==
|
|
IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
|
|
for (i = 0; i < hw->port_num; i++) {
|
|
/* Clear NIC side TX statistics counters */
|
|
ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
|
|
|
|
/* Clear NIC side RX statistics counters */
|
|
ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
|
|
|
|
/* Clear line side TX statistics counters */
|
|
ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
|
|
|
|
/* Clear line side RX statistics counters */
|
|
ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int ipn3ke_vswitch_probe(struct rte_afu_device *afu_dev)
|
|
{
|
|
char name[RTE_ETH_NAME_MAX_LEN];
|
|
struct ipn3ke_hw *hw;
|
|
struct rte_eth_dev *i40e_eth;
|
|
struct ifpga_rawdev *ifpga_dev;
|
|
uint16_t port_id;
|
|
int i, j, retval;
|
|
char *fvl_bdf;
|
|
|
|
/* check if the AFU device has been probed already */
|
|
/* allocate shared mcp_vswitch structure */
|
|
if (!afu_dev->shared.data) {
|
|
snprintf(name, sizeof(name), "net_%s_hw",
|
|
afu_dev->device.name);
|
|
hw = rte_zmalloc_socket(name,
|
|
sizeof(struct ipn3ke_hw),
|
|
RTE_CACHE_LINE_SIZE,
|
|
afu_dev->device.numa_node);
|
|
if (!hw) {
|
|
IPN3KE_AFU_PMD_ERR("failed to allocate hardwart data");
|
|
retval = -ENOMEM;
|
|
return -ENOMEM;
|
|
}
|
|
afu_dev->shared.data = hw;
|
|
|
|
rte_spinlock_init(&afu_dev->shared.lock);
|
|
} else {
|
|
hw = afu_dev->shared.data;
|
|
}
|
|
|
|
retval = ipn3ke_hw_init(afu_dev, hw);
|
|
if (retval)
|
|
return retval;
|
|
|
|
if (ipn3ke_bridge_func.get_ifpga_rawdev == NULL)
|
|
return -ENOMEM;
|
|
ifpga_dev = ipn3ke_bridge_func.get_ifpga_rawdev(hw->rawdev);
|
|
if (!ifpga_dev)
|
|
IPN3KE_AFU_PMD_ERR("failed to find ifpga_device.");
|
|
|
|
/* probe representor ports */
|
|
j = 0;
|
|
for (i = 0; i < hw->port_num; i++) {
|
|
struct ipn3ke_rpst rpst = {
|
|
.port_id = i,
|
|
.switch_domain_id = hw->switch_domain_id,
|
|
.hw = hw
|
|
};
|
|
|
|
/* representor port net_bdf_port */
|
|
snprintf(name, sizeof(name), "net_%s_representor_%d",
|
|
afu_dev->device.name, i);
|
|
|
|
for (; j < 8; j++) {
|
|
fvl_bdf = ifpga_dev->fvl_bdf[j];
|
|
retval = rte_eth_dev_get_port_by_name(fvl_bdf,
|
|
&port_id);
|
|
if (retval) {
|
|
continue;
|
|
} else {
|
|
i40e_eth = &rte_eth_devices[port_id];
|
|
rpst.i40e_pf_eth = i40e_eth;
|
|
rpst.i40e_pf_eth_port_id = port_id;
|
|
|
|
j++;
|
|
break;
|
|
}
|
|
}
|
|
|
|
retval = rte_eth_dev_create(&afu_dev->device, name,
|
|
sizeof(struct ipn3ke_rpst), NULL, NULL,
|
|
ipn3ke_rpst_init, &rpst);
|
|
|
|
if (retval)
|
|
IPN3KE_AFU_PMD_ERR("failed to create ipn3ke representor %s.",
|
|
name);
|
|
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ipn3ke_vswitch_remove(struct rte_afu_device *afu_dev)
|
|
{
|
|
char name[RTE_ETH_NAME_MAX_LEN];
|
|
struct ipn3ke_hw *hw;
|
|
struct rte_eth_dev *ethdev;
|
|
int i, ret;
|
|
|
|
hw = afu_dev->shared.data;
|
|
|
|
/* remove representor ports */
|
|
for (i = 0; i < hw->port_num; i++) {
|
|
/* representor port net_bdf_port */
|
|
snprintf(name, sizeof(name), "net_%s_representor_%d",
|
|
afu_dev->device.name, i);
|
|
|
|
ethdev = rte_eth_dev_allocated(afu_dev->device.name);
|
|
if (!ethdev)
|
|
return -ENODEV;
|
|
|
|
rte_eth_dev_destroy(ethdev, ipn3ke_rpst_uninit);
|
|
}
|
|
|
|
ret = rte_eth_switch_domain_free(hw->switch_domain_id);
|
|
if (ret)
|
|
IPN3KE_AFU_PMD_WARN("failed to free switch domain: %d", ret);
|
|
|
|
/* hw uninit*/
|
|
ipn3ke_hw_uninit(hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct rte_afu_driver afu_ipn3ke_driver = {
|
|
.id_table = afu_uuid_ipn3ke_map,
|
|
.probe = ipn3ke_vswitch_probe,
|
|
.remove = ipn3ke_vswitch_remove,
|
|
};
|
|
|
|
RTE_PMD_REGISTER_AFU(net_ipn3ke_afu, afu_ipn3ke_driver);
|
|
RTE_LOG_REGISTER(ipn3ke_afu_logtype, pmd.afu.ipn3ke, NOTICE);
|