c7e6ab78f4
Registered cn9k and cn10k for asymmetric crypto autotest. Documentation and release notes are also updated. Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
240 lines
5.7 KiB
ReStructuredText
240 lines
5.7 KiB
ReStructuredText
.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(c) 2021 Marvell.
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Marvell cnxk Crypto Poll Mode Driver
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====================================
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The cnxk crypto poll mode driver provides support for offloading
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cryptographic operations to cryptographic accelerator units on the
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**Marvell OCTEON cnxk** SoC family.
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The cnxk crypto PMD code is organized into different sets of files.
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The file names starting with cn9k and cn10k provides support for CN9XX
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and CN10XX respectively. The common code between the SoCs is present
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in file names starting with cnxk.
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More information about OCTEON cnxk SoCs may be obtained from `<https://www.marvell.com>`_
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Supported OCTEON cnxk SoCs
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--------------------------
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- CN9XX
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- CN10XX
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Features
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--------
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The OCTEON cnxk crypto PMD has support for:
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Symmetric Crypto Algorithms
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Cipher algorithms:
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* ``RTE_CRYPTO_CIPHER_NULL``
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* ``RTE_CRYPTO_CIPHER_3DES_CBC``
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* ``RTE_CRYPTO_CIPHER_3DES_ECB``
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* ``RTE_CRYPTO_CIPHER_AES_CBC``
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* ``RTE_CRYPTO_CIPHER_AES_CTR``
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* ``RTE_CRYPTO_CIPHER_AES_XTS``
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* ``RTE_CRYPTO_CIPHER_DES_CBC``
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* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
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* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
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* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
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Hash algorithms:
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* ``RTE_CRYPTO_AUTH_NULL``
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* ``RTE_CRYPTO_AUTH_AES_GMAC``
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* ``RTE_CRYPTO_AUTH_KASUMI_F9``
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* ``RTE_CRYPTO_AUTH_MD5``
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* ``RTE_CRYPTO_AUTH_MD5_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA1``
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* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA224``
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* ``RTE_CRYPTO_AUTH_SHA224_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA256``
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* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA384``
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* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
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* ``RTE_CRYPTO_AUTH_SHA512``
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* ``RTE_CRYPTO_AUTH_SHA512_HMAC``
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* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
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* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
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AEAD algorithms:
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* ``RTE_CRYPTO_AEAD_AES_GCM``
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* ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``
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Asymmetric Crypto Algorithms
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* ``RTE_CRYPTO_ASYM_XFORM_RSA``
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* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
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Installation
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------------
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The OCTEON cnxk crypto PMD may be compiled natively on an OCTEON cnxk platform
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or cross-compiled on an x86 platform.
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Refer to :doc:`../platform/cnxk` for instructions to build your DPDK
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application.
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.. note::
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The OCTEON cnxk crypto PMD uses services from the kernel mode OCTEON cnxk
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crypto PF driver in linux. This driver is included in the OCTEON TX SDK.
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Initialization
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--------------
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``CN9K Initialization``
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List the CPT PF devices available on cn9k platform:
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.. code-block:: console
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lspci -d:a0fd
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``a0fd`` is the CPT PF device id. You should see output similar to:
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.. code-block:: console
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0002:10:00.0 Class 1080: Device 177d:a0fd
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Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
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.. code-block:: console
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echo 1 > /sys/bus/pci/devices/0002:10:00.0/sriov_numvfs
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Bind the CPT VF device to the vfio_pci driver:
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.. code-block:: console
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cd <dpdk directory>
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./usertools/dpdk-devbind.py -u 0002:10:00.1
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./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1
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.. note::
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* For CN98xx SoC, it is recommended to use even and odd DBDF VFs to achieve
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higher performance as even VF uses one crypto engine and odd one uses
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another crypto engine.
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* Ensure that sufficient huge pages are available for your application::
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dpdk-hugepages.py --setup 4G --pagesize 512M
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Refer to :ref:`linux_gsg_hugepages` for more details.
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``CN10K Initialization``
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List the CPT PF devices available on cn10k platform:
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.. code-block:: console
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lspci -d:a0f2
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``a0f2`` is the CPT PF device id. You should see output similar to:
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.. code-block:: console
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0002:20:00.0 Class 1080: Device 177d:a0f2
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Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
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.. code-block:: console
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echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs
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Bind the CPT VF device to the vfio_pci driver:
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.. code-block:: console
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cd <dpdk directory>
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./usertools/dpdk-devbind.py -u 0002:20:00.1
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./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1
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Debugging Options
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-----------------
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.. _table_octeon_cnxk_crypto_debug_options:
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.. table:: OCTEON cnxk crypto PMD debug options
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+---+------------+-------------------------------------------------------+
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| # | Component | EAL log command |
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+===+============+=======================================================+
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| 1 | CPT | --log-level='pmd\.crypto\.cnxk,8' |
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+---+------------+-------------------------------------------------------+
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Testing
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-------
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The symmetric crypto operations on OCTEON cnxk crypto PMD may be verified by
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running the test application:
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``CN9K``
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.. code-block:: console
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./dpdk-test
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RTE>>cryptodev_cn9k_autotest
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``CN10K``
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.. code-block:: console
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./dpdk-test
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RTE>>cryptodev_cn10k_autotest
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The asymmetric crypto operations on OCTEON cnxk crypto PMD may be verified by
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running the test application:
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``CN9K``
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.. code-block:: console
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./dpdk-test
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RTE>>cryptodev_cn9k_asym_autotest
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``CN10K``
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.. code-block:: console
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./dpdk-test
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RTE>>cryptodev_cn10k_asym_autotest
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Lookaside IPsec Support
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-----------------------
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The OCTEON cnxk SoCs can accelerate IPsec traffic in lookaside protocol mode,
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with its **cryptographic accelerator (CPT)**. ``OCTEON cnxk crypto PMD`` implements
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this as an ``RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL`` offload.
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Refer to :doc:`../prog_guide/rte_security` for more details on protocol offloads.
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This feature can be tested with ipsec-secgw sample application.
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Supported OCTEON cnxk SoCs
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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- CN10XX
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Features supported
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~~~~~~~~~~~~~~~~~~
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* IPv4
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* ESP
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* Tunnel mode
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* AES-128/192/256-GCM
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Limitations
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-----------
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Multiple lcores may not operate on the same crypto queue pair. The lcore that
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enqueues to a queue pair is the one that must dequeue from it.
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