Mempool elements are by default aligned to CACHELINE_SIZE.
In CN10K cacheline size is 64B but the RoC requires buffers to be
aligned to 128B.
Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
128 bytes.
Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")
Cc: stable@dpdk.org
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
3e97fa671d