a0147be547
Xilinx acquired Solarflare in 2019. Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com> Acked-by: James Fox <jamesfox@xilinx.com>
966 lines
21 KiB
C
966 lines
21 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright(c) 2019-2020 Xilinx, Inc.
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* Copyright(c) 2007-2019 Solarflare Communications Inc.
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*/
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#include "efx.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_SIENA
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static __checkReturn efx_rc_t
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siena_mac_multicast_list_set(
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__in efx_nic_t *enp);
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#endif /* EFSYS_OPT_SIENA */
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#if EFSYS_OPT_SIENA
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static const efx_mac_ops_t __efx_mac_siena_ops = {
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siena_mac_poll, /* emo_poll */
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siena_mac_up, /* emo_up */
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siena_mac_reconfigure, /* emo_addr_set */
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siena_mac_reconfigure, /* emo_pdu_set */
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siena_mac_pdu_get, /* emo_pdu_get */
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siena_mac_reconfigure, /* emo_reconfigure */
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siena_mac_multicast_list_set, /* emo_multicast_list_set */
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NULL, /* emo_filter_set_default_rxq */
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NULL, /* emo_filter_default_rxq_clear */
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#if EFSYS_OPT_LOOPBACK
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siena_mac_loopback_set, /* emo_loopback_set */
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#endif /* EFSYS_OPT_LOOPBACK */
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#if EFSYS_OPT_MAC_STATS
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siena_mac_stats_get_mask, /* emo_stats_get_mask */
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efx_mcdi_mac_stats_clear, /* emo_stats_clear */
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efx_mcdi_mac_stats_upload, /* emo_stats_upload */
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efx_mcdi_mac_stats_periodic, /* emo_stats_periodic */
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siena_mac_stats_update /* emo_stats_update */
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#endif /* EFSYS_OPT_MAC_STATS */
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};
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#endif /* EFSYS_OPT_SIENA */
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#if EFX_OPTS_EF10()
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static const efx_mac_ops_t __efx_mac_ef10_ops = {
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ef10_mac_poll, /* emo_poll */
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ef10_mac_up, /* emo_up */
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ef10_mac_addr_set, /* emo_addr_set */
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ef10_mac_pdu_set, /* emo_pdu_set */
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ef10_mac_pdu_get, /* emo_pdu_get */
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ef10_mac_reconfigure, /* emo_reconfigure */
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ef10_mac_multicast_list_set, /* emo_multicast_list_set */
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ef10_mac_filter_default_rxq_set, /* emo_filter_default_rxq_set */
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ef10_mac_filter_default_rxq_clear,
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/* emo_filter_default_rxq_clear */
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#if EFSYS_OPT_LOOPBACK
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ef10_mac_loopback_set, /* emo_loopback_set */
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#endif /* EFSYS_OPT_LOOPBACK */
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#if EFSYS_OPT_MAC_STATS
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ef10_mac_stats_get_mask, /* emo_stats_get_mask */
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efx_mcdi_mac_stats_clear, /* emo_stats_clear */
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efx_mcdi_mac_stats_upload, /* emo_stats_upload */
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efx_mcdi_mac_stats_periodic, /* emo_stats_periodic */
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ef10_mac_stats_update /* emo_stats_update */
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#endif /* EFSYS_OPT_MAC_STATS */
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};
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#endif /* EFX_OPTS_EF10() */
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__checkReturn efx_rc_t
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efx_mac_pdu_set(
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__in efx_nic_t *enp,
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__in size_t pdu)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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uint32_t old_pdu;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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EFSYS_ASSERT(emop != NULL);
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if (pdu < EFX_MAC_PDU_MIN) {
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rc = EINVAL;
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goto fail1;
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}
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if (pdu > EFX_MAC_PDU_MAX) {
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rc = EINVAL;
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goto fail2;
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}
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old_pdu = epp->ep_mac_pdu;
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epp->ep_mac_pdu = (uint32_t)pdu;
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if ((rc = emop->emo_pdu_set(enp)) != 0)
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goto fail3;
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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epp->ep_mac_pdu = old_pdu;
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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efx_mac_pdu_get(
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__in efx_nic_t *enp,
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__out size_t *pdu)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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efx_rc_t rc;
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if ((rc = emop->emo_pdu_get(enp, pdu)) != 0)
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goto fail1;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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efx_mac_addr_set(
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__in efx_nic_t *enp,
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__in uint8_t *addr)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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uint8_t old_addr[6];
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uint32_t oui;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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if (EFX_MAC_ADDR_IS_MULTICAST(addr)) {
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rc = EINVAL;
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goto fail1;
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}
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oui = addr[0] << 16 | addr[1] << 8 | addr[2];
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if (oui == 0x000000) {
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rc = EINVAL;
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goto fail2;
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}
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EFX_MAC_ADDR_COPY(old_addr, epp->ep_mac_addr);
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EFX_MAC_ADDR_COPY(epp->ep_mac_addr, addr);
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if ((rc = emop->emo_addr_set(enp)) != 0)
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goto fail3;
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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EFX_MAC_ADDR_COPY(epp->ep_mac_addr, old_addr);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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efx_mac_filter_set(
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__in efx_nic_t *enp,
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__in boolean_t all_unicst,
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__in boolean_t mulcst,
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__in boolean_t all_mulcst,
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__in boolean_t brdcst)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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boolean_t old_all_unicst;
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boolean_t old_mulcst;
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boolean_t old_all_mulcst;
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boolean_t old_brdcst;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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old_all_unicst = epp->ep_all_unicst;
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old_mulcst = epp->ep_mulcst;
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old_all_mulcst = epp->ep_all_mulcst;
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old_brdcst = epp->ep_brdcst;
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epp->ep_all_unicst = all_unicst;
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epp->ep_mulcst = mulcst;
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epp->ep_all_mulcst = all_mulcst;
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epp->ep_brdcst = brdcst;
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if ((rc = emop->emo_reconfigure(enp)) != 0)
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goto fail1;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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epp->ep_all_unicst = old_all_unicst;
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epp->ep_mulcst = old_mulcst;
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epp->ep_all_mulcst = old_all_mulcst;
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epp->ep_brdcst = old_brdcst;
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return (rc);
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}
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void
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efx_mac_filter_get_all_ucast_mcast(
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__in efx_nic_t *enp,
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__out boolean_t *all_unicst,
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__out boolean_t *all_mulcst)
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{
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efx_port_t *epp = &(enp->en_port);
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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*all_unicst = epp->ep_all_unicst_inserted;
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*all_mulcst = epp->ep_all_mulcst_inserted;
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}
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__checkReturn efx_rc_t
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efx_mac_drain(
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__in efx_nic_t *enp,
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__in boolean_t enabled)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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EFSYS_ASSERT(emop != NULL);
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if (epp->ep_mac_drain == enabled)
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return (0);
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epp->ep_mac_drain = enabled;
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if ((rc = emop->emo_reconfigure(enp)) != 0)
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goto fail1;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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efx_mac_up(
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__in efx_nic_t *enp,
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__out boolean_t *mac_upp)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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if ((rc = emop->emo_up(enp, mac_upp)) != 0)
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goto fail1;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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efx_mac_fcntl_set(
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__in efx_nic_t *enp,
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__in unsigned int fcntl,
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__in boolean_t autoneg)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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const efx_phy_ops_t *epop = epp->ep_epop;
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unsigned int old_fcntl;
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boolean_t old_autoneg;
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unsigned int old_adv_cap;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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if ((fcntl & ~(EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE)) != 0) {
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rc = EINVAL;
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goto fail1;
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}
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/*
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* Ignore a request to set flow control auto-negotiation
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* if the PHY doesn't support it.
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*/
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if (~epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
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autoneg = B_FALSE;
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old_fcntl = epp->ep_fcntl;
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old_autoneg = epp->ep_fcntl_autoneg;
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old_adv_cap = epp->ep_adv_cap_mask;
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epp->ep_fcntl = fcntl;
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epp->ep_fcntl_autoneg = autoneg;
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/*
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* Always encode the flow control settings in the advertised
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* capabilities even if we are not trying to auto-negotiate
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* them and reconfigure both the PHY and the MAC.
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*/
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if (fcntl & EFX_FCNTL_RESPOND)
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epp->ep_adv_cap_mask |= (1 << EFX_PHY_CAP_PAUSE |
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1 << EFX_PHY_CAP_ASYM);
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else
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epp->ep_adv_cap_mask &= ~(1 << EFX_PHY_CAP_PAUSE |
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1 << EFX_PHY_CAP_ASYM);
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if (fcntl & EFX_FCNTL_GENERATE)
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epp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM);
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if ((rc = epop->epo_reconfigure(enp)) != 0)
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goto fail2;
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if ((rc = emop->emo_reconfigure(enp)) != 0)
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goto fail3;
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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EFSYS_PROBE(fail2);
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epp->ep_fcntl = old_fcntl;
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epp->ep_fcntl_autoneg = old_autoneg;
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epp->ep_adv_cap_mask = old_adv_cap;
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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void
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efx_mac_fcntl_get(
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__in efx_nic_t *enp,
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__out unsigned int *fcntl_wantedp,
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__out unsigned int *fcntl_linkp)
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{
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efx_port_t *epp = &(enp->en_port);
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unsigned int wanted = 0;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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/*
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* Decode the requested flow control settings from the PHY
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* advertised capabilities.
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*/
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if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_PAUSE))
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wanted = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
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if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM))
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wanted ^= EFX_FCNTL_GENERATE;
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*fcntl_linkp = epp->ep_fcntl;
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*fcntl_wantedp = wanted;
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}
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__checkReturn efx_rc_t
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efx_mac_multicast_list_set(
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__in efx_nic_t *enp,
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__in_ecount(6*count) uint8_t const *addrs,
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__in int count)
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{
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efx_port_t *epp = &(enp->en_port);
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const efx_mac_ops_t *emop = epp->ep_emop;
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uint8_t *old_mulcst_addr_list = NULL;
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uint32_t old_mulcst_addr_count;
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efx_rc_t rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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if (count > EFX_MAC_MULTICAST_LIST_MAX) {
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rc = EINVAL;
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goto fail1;
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}
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old_mulcst_addr_count = epp->ep_mulcst_addr_count;
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if (old_mulcst_addr_count > 0) {
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/* Allocate memory to store old list (instead of using stack) */
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EFSYS_KMEM_ALLOC(enp->en_esip,
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old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
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old_mulcst_addr_list);
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if (old_mulcst_addr_list == NULL) {
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rc = ENOMEM;
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goto fail2;
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}
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/* Save the old list in case we need to rollback */
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memcpy(old_mulcst_addr_list, epp->ep_mulcst_addr_list,
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old_mulcst_addr_count * EFX_MAC_ADDR_LEN);
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}
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/* Store the new list */
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memcpy(epp->ep_mulcst_addr_list, addrs,
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count * EFX_MAC_ADDR_LEN);
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epp->ep_mulcst_addr_count = count;
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if ((rc = emop->emo_multicast_list_set(enp)) != 0)
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goto fail3;
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if (old_mulcst_addr_count > 0) {
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EFSYS_KMEM_FREE(enp->en_esip,
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old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
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old_mulcst_addr_list);
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}
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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/* Restore original list on failure */
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epp->ep_mulcst_addr_count = old_mulcst_addr_count;
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if (old_mulcst_addr_count > 0) {
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memcpy(epp->ep_mulcst_addr_list, old_mulcst_addr_list,
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old_mulcst_addr_count * EFX_MAC_ADDR_LEN);
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EFSYS_KMEM_FREE(enp->en_esip,
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old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
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old_mulcst_addr_list);
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}
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, efx_rc_t, rc);
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return (rc);
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}
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__checkReturn efx_rc_t
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efx_mac_filter_default_rxq_set(
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__in efx_nic_t *enp,
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__in efx_rxq_t *erp,
|
|
__in boolean_t using_rss)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
efx_rc_t rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
if (emop->emo_filter_default_rxq_set != NULL) {
|
|
rc = emop->emo_filter_default_rxq_set(enp, erp, using_rss);
|
|
if (rc != 0)
|
|
goto fail1;
|
|
}
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
void
|
|
efx_mac_filter_default_rxq_clear(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
if (emop->emo_filter_default_rxq_clear != NULL)
|
|
emop->emo_filter_default_rxq_clear(enp);
|
|
}
|
|
|
|
|
|
#if EFSYS_OPT_MAC_STATS
|
|
|
|
#if EFSYS_OPT_NAMES
|
|
|
|
/* START MKCONFIG GENERATED EfxMacStatNamesBlock 1a45a82fcfb30c1b */
|
|
static const char * const __efx_mac_stat_name[] = {
|
|
"rx_octets",
|
|
"rx_pkts",
|
|
"rx_unicst_pkts",
|
|
"rx_multicst_pkts",
|
|
"rx_brdcst_pkts",
|
|
"rx_pause_pkts",
|
|
"rx_le_64_pkts",
|
|
"rx_65_to_127_pkts",
|
|
"rx_128_to_255_pkts",
|
|
"rx_256_to_511_pkts",
|
|
"rx_512_to_1023_pkts",
|
|
"rx_1024_to_15xx_pkts",
|
|
"rx_ge_15xx_pkts",
|
|
"rx_errors",
|
|
"rx_fcs_errors",
|
|
"rx_drop_events",
|
|
"rx_false_carrier_errors",
|
|
"rx_symbol_errors",
|
|
"rx_align_errors",
|
|
"rx_internal_errors",
|
|
"rx_jabber_pkts",
|
|
"rx_lane0_char_err",
|
|
"rx_lane1_char_err",
|
|
"rx_lane2_char_err",
|
|
"rx_lane3_char_err",
|
|
"rx_lane0_disp_err",
|
|
"rx_lane1_disp_err",
|
|
"rx_lane2_disp_err",
|
|
"rx_lane3_disp_err",
|
|
"rx_match_fault",
|
|
"rx_nodesc_drop_cnt",
|
|
"tx_octets",
|
|
"tx_pkts",
|
|
"tx_unicst_pkts",
|
|
"tx_multicst_pkts",
|
|
"tx_brdcst_pkts",
|
|
"tx_pause_pkts",
|
|
"tx_le_64_pkts",
|
|
"tx_65_to_127_pkts",
|
|
"tx_128_to_255_pkts",
|
|
"tx_256_to_511_pkts",
|
|
"tx_512_to_1023_pkts",
|
|
"tx_1024_to_15xx_pkts",
|
|
"tx_ge_15xx_pkts",
|
|
"tx_errors",
|
|
"tx_sgl_col_pkts",
|
|
"tx_mult_col_pkts",
|
|
"tx_ex_col_pkts",
|
|
"tx_late_col_pkts",
|
|
"tx_def_pkts",
|
|
"tx_ex_def_pkts",
|
|
"pm_trunc_bb_overflow",
|
|
"pm_discard_bb_overflow",
|
|
"pm_trunc_vfifo_full",
|
|
"pm_discard_vfifo_full",
|
|
"pm_trunc_qbb",
|
|
"pm_discard_qbb",
|
|
"pm_discard_mapping",
|
|
"rxdp_q_disabled_pkts",
|
|
"rxdp_di_dropped_pkts",
|
|
"rxdp_streaming_pkts",
|
|
"rxdp_hlb_fetch",
|
|
"rxdp_hlb_wait",
|
|
"vadapter_rx_unicast_packets",
|
|
"vadapter_rx_unicast_bytes",
|
|
"vadapter_rx_multicast_packets",
|
|
"vadapter_rx_multicast_bytes",
|
|
"vadapter_rx_broadcast_packets",
|
|
"vadapter_rx_broadcast_bytes",
|
|
"vadapter_rx_bad_packets",
|
|
"vadapter_rx_bad_bytes",
|
|
"vadapter_rx_overflow",
|
|
"vadapter_tx_unicast_packets",
|
|
"vadapter_tx_unicast_bytes",
|
|
"vadapter_tx_multicast_packets",
|
|
"vadapter_tx_multicast_bytes",
|
|
"vadapter_tx_broadcast_packets",
|
|
"vadapter_tx_broadcast_bytes",
|
|
"vadapter_tx_bad_packets",
|
|
"vadapter_tx_bad_bytes",
|
|
"vadapter_tx_overflow",
|
|
"fec_uncorrected_errors",
|
|
"fec_corrected_errors",
|
|
"fec_corrected_symbols_lane0",
|
|
"fec_corrected_symbols_lane1",
|
|
"fec_corrected_symbols_lane2",
|
|
"fec_corrected_symbols_lane3",
|
|
"ctpio_vi_busy_fallback",
|
|
"ctpio_long_write_success",
|
|
"ctpio_missing_dbell_fail",
|
|
"ctpio_overflow_fail",
|
|
"ctpio_underflow_fail",
|
|
"ctpio_timeout_fail",
|
|
"ctpio_noncontig_wr_fail",
|
|
"ctpio_frm_clobber_fail",
|
|
"ctpio_invalid_wr_fail",
|
|
"ctpio_vi_clobber_fallback",
|
|
"ctpio_unqualified_fallback",
|
|
"ctpio_runt_fallback",
|
|
"ctpio_success",
|
|
"ctpio_fallback",
|
|
"ctpio_poison",
|
|
"ctpio_erase",
|
|
"rxdp_scatter_disabled_trunc",
|
|
"rxdp_hlb_idle",
|
|
"rxdp_hlb_timeout",
|
|
};
|
|
/* END MKCONFIG GENERATED EfxMacStatNamesBlock */
|
|
|
|
__checkReturn const char *
|
|
efx_mac_stat_name(
|
|
__in efx_nic_t *enp,
|
|
__in unsigned int id)
|
|
{
|
|
_NOTE(ARGUNUSED(enp))
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
|
|
EFSYS_ASSERT3U(id, <, EFX_MAC_NSTATS);
|
|
return (__efx_mac_stat_name[id]);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_NAMES */
|
|
|
|
static efx_rc_t
|
|
efx_mac_stats_mask_add_range(
|
|
__inout_bcount(mask_size) uint32_t *maskp,
|
|
__in size_t mask_size,
|
|
__in const struct efx_mac_stats_range *rngp)
|
|
{
|
|
unsigned int mask_npages = mask_size / sizeof (*maskp);
|
|
unsigned int el;
|
|
unsigned int el_min;
|
|
unsigned int el_max;
|
|
unsigned int low;
|
|
unsigned int high;
|
|
unsigned int width;
|
|
efx_rc_t rc;
|
|
|
|
if ((mask_npages * EFX_MAC_STATS_MASK_BITS_PER_PAGE) <=
|
|
(unsigned int)rngp->last) {
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
|
|
EFSYS_ASSERT3U(rngp->first, <=, rngp->last);
|
|
EFSYS_ASSERT3U(rngp->last, <, EFX_MAC_NSTATS);
|
|
|
|
for (el = 0; el < mask_npages; ++el) {
|
|
el_min = el * EFX_MAC_STATS_MASK_BITS_PER_PAGE;
|
|
el_max =
|
|
el_min + (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1);
|
|
if ((unsigned int)rngp->first > el_max ||
|
|
(unsigned int)rngp->last < el_min)
|
|
continue;
|
|
low = MAX((unsigned int)rngp->first, el_min);
|
|
high = MIN((unsigned int)rngp->last, el_max);
|
|
width = high - low + 1;
|
|
maskp[el] |=
|
|
(width == EFX_MAC_STATS_MASK_BITS_PER_PAGE) ?
|
|
(~0ULL) : (((1ULL << width) - 1) << (low - el_min));
|
|
}
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
efx_rc_t
|
|
efx_mac_stats_mask_add_ranges(
|
|
__inout_bcount(mask_size) uint32_t *maskp,
|
|
__in size_t mask_size,
|
|
__in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
|
|
__in unsigned int rng_count)
|
|
{
|
|
unsigned int i;
|
|
efx_rc_t rc;
|
|
|
|
for (i = 0; i < rng_count; ++i) {
|
|
if ((rc = efx_mac_stats_mask_add_range(maskp, mask_size,
|
|
&rngp[i])) != 0)
|
|
goto fail1;
|
|
}
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn efx_rc_t
|
|
efx_mac_stats_get_mask(
|
|
__in efx_nic_t *enp,
|
|
__out_bcount(mask_size) uint32_t *maskp,
|
|
__in size_t mask_size)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
efx_rc_t rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
|
|
EFSYS_ASSERT(maskp != NULL);
|
|
EFSYS_ASSERT(mask_size % sizeof (maskp[0]) == 0);
|
|
|
|
(void) memset(maskp, 0, mask_size);
|
|
|
|
if ((rc = emop->emo_stats_get_mask(enp, maskp, mask_size)) != 0)
|
|
goto fail1;
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn efx_rc_t
|
|
efx_mac_stats_clear(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
efx_rc_t rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
EFSYS_ASSERT(emop != NULL);
|
|
|
|
if ((rc = emop->emo_stats_clear(enp)) != 0)
|
|
goto fail1;
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn efx_rc_t
|
|
efx_mac_stats_upload(
|
|
__in efx_nic_t *enp,
|
|
__in efsys_mem_t *esmp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
efx_rc_t rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
EFSYS_ASSERT(emop != NULL);
|
|
|
|
if ((rc = emop->emo_stats_upload(enp, esmp)) != 0)
|
|
goto fail1;
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn efx_rc_t
|
|
efx_mac_stats_periodic(
|
|
__in efx_nic_t *enp,
|
|
__in efsys_mem_t *esmp,
|
|
__in uint16_t period_ms,
|
|
__in boolean_t events)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
efx_rc_t rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
EFSYS_ASSERT(emop != NULL);
|
|
|
|
if (emop->emo_stats_periodic == NULL) {
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
|
|
if ((rc = emop->emo_stats_periodic(enp, esmp, period_ms, events)) != 0)
|
|
goto fail2;
|
|
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
|
|
__checkReturn efx_rc_t
|
|
efx_mac_stats_update(
|
|
__in efx_nic_t *enp,
|
|
__in efsys_mem_t *esmp,
|
|
__inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *essp,
|
|
__inout_opt uint32_t *generationp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
efx_rc_t rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
EFSYS_ASSERT(emop != NULL);
|
|
|
|
rc = emop->emo_stats_update(enp, esmp, essp, generationp);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_MAC_STATS */
|
|
|
|
__checkReturn efx_rc_t
|
|
efx_mac_select(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_mac_type_t type = EFX_MAC_INVALID;
|
|
const efx_mac_ops_t *emop;
|
|
int rc = EINVAL;
|
|
|
|
switch (enp->en_family) {
|
|
#if EFSYS_OPT_SIENA
|
|
case EFX_FAMILY_SIENA:
|
|
emop = &__efx_mac_siena_ops;
|
|
type = EFX_MAC_SIENA;
|
|
break;
|
|
#endif /* EFSYS_OPT_SIENA */
|
|
|
|
#if EFSYS_OPT_HUNTINGTON
|
|
case EFX_FAMILY_HUNTINGTON:
|
|
emop = &__efx_mac_ef10_ops;
|
|
type = EFX_MAC_HUNTINGTON;
|
|
break;
|
|
#endif /* EFSYS_OPT_HUNTINGTON */
|
|
|
|
#if EFSYS_OPT_MEDFORD
|
|
case EFX_FAMILY_MEDFORD:
|
|
emop = &__efx_mac_ef10_ops;
|
|
type = EFX_MAC_MEDFORD;
|
|
break;
|
|
#endif /* EFSYS_OPT_MEDFORD */
|
|
|
|
#if EFSYS_OPT_MEDFORD2
|
|
case EFX_FAMILY_MEDFORD2:
|
|
emop = &__efx_mac_ef10_ops;
|
|
type = EFX_MAC_MEDFORD2;
|
|
break;
|
|
#endif /* EFSYS_OPT_MEDFORD2 */
|
|
|
|
default:
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
|
|
EFSYS_ASSERT(type != EFX_MAC_INVALID);
|
|
EFSYS_ASSERT3U(type, <, EFX_MAC_NTYPES);
|
|
EFSYS_ASSERT(emop != NULL);
|
|
|
|
epp->ep_emop = emop;
|
|
epp->ep_mac_type = type;
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
|
|
#if EFSYS_OPT_SIENA
|
|
|
|
#define EFX_MAC_HASH_BITS (1 << 8)
|
|
|
|
/* Compute the multicast hash as used on Falcon and Siena. */
|
|
static void
|
|
siena_mac_multicast_hash_compute(
|
|
__in_ecount(6*count) uint8_t const *addrs,
|
|
__in int count,
|
|
__out efx_oword_t *hash_low,
|
|
__out efx_oword_t *hash_high)
|
|
{
|
|
uint32_t crc, index;
|
|
int i;
|
|
|
|
EFSYS_ASSERT(hash_low != NULL);
|
|
EFSYS_ASSERT(hash_high != NULL);
|
|
|
|
EFX_ZERO_OWORD(*hash_low);
|
|
EFX_ZERO_OWORD(*hash_high);
|
|
|
|
for (i = 0; i < count; i++) {
|
|
/* Calculate hash bucket (IEEE 802.3 CRC32 of the MAC addr) */
|
|
crc = efx_crc32_calculate(0xffffffff, addrs, EFX_MAC_ADDR_LEN);
|
|
index = crc % EFX_MAC_HASH_BITS;
|
|
if (index < 128) {
|
|
EFX_SET_OWORD_BIT(*hash_low, index);
|
|
} else {
|
|
EFX_SET_OWORD_BIT(*hash_high, index - 128);
|
|
}
|
|
|
|
addrs += EFX_MAC_ADDR_LEN;
|
|
}
|
|
}
|
|
|
|
static __checkReturn efx_rc_t
|
|
siena_mac_multicast_list_set(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
const efx_mac_ops_t *emop = epp->ep_emop;
|
|
efx_oword_t old_hash[2];
|
|
efx_rc_t rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash));
|
|
|
|
siena_mac_multicast_hash_compute(
|
|
epp->ep_mulcst_addr_list,
|
|
epp->ep_mulcst_addr_count,
|
|
&epp->ep_multicst_hash[0],
|
|
&epp->ep_multicst_hash[1]);
|
|
|
|
if ((rc = emop->emo_reconfigure(enp)) != 0)
|
|
goto fail1;
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, efx_rc_t, rc);
|
|
|
|
memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash));
|
|
|
|
return (rc);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_SIENA */
|