72514b5d55
The parameter tx_free_thresh is not consistent between the drivers: some use it as rte_eth_tx_burst() requires, some release buffers when the number of free descriptors drop below this value. Let's use it as most fast-path code does, which is the latter, and update comments throughout the code to reflect that. Signed-off-by: Zoltan Kiss <zoltan.kiss@linaro.org> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
213 lines
8.3 KiB
C
213 lines
8.3 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _I40E_RXTX_H_
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#define _I40E_RXTX_H_
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/**
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* 32 bits tx flags, high 16 bits for L2TAG1 (VLAN),
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* low 16 bits for others.
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*/
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#define I40E_TX_FLAG_L2TAG1_SHIFT 16
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#define I40E_TX_FLAG_L2TAG1_MASK 0xffff0000
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#define I40E_TX_FLAG_CSUM ((uint32_t)(1 << 0))
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#define I40E_TX_FLAG_INSERT_VLAN ((uint32_t)(1 << 1))
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#define I40E_TX_FLAG_TSYN ((uint32_t)(1 << 2))
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#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
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#define RTE_PMD_I40E_RX_MAX_BURST 32
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#endif
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#define I40E_RXBUF_SZ_1024 1024
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#define I40E_RXBUF_SZ_2048 2048
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enum i40e_header_split_mode {
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i40e_header_split_none = 0,
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i40e_header_split_enabled = 1,
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i40e_header_split_always = 2,
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i40e_header_split_reserved
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};
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#define I40E_HEADER_SPLIT_NONE ((uint8_t)0)
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#define I40E_HEADER_SPLIT_L2 ((uint8_t)(1 << 0))
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#define I40E_HEADER_SPLIT_IP ((uint8_t)(1 << 1))
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#define I40E_HEADER_SPLIT_UDP_TCP ((uint8_t)(1 << 2))
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#define I40E_HEADER_SPLIT_SCTP ((uint8_t)(1 << 3))
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#define I40E_HEADER_SPLIT_ALL (I40E_HEADER_SPLIT_L2 | \
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I40E_HEADER_SPLIT_IP | \
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I40E_HEADER_SPLIT_UDP_TCP | \
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I40E_HEADER_SPLIT_SCTP)
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/* HW desc structure, both 16-byte and 32-byte types are supported */
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#ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
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#define i40e_rx_desc i40e_16byte_rx_desc
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#else
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#define i40e_rx_desc i40e_32byte_rx_desc
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#endif
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struct i40e_rx_entry {
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struct rte_mbuf *mbuf;
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};
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/*
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* Structure associated with each RX queue.
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*/
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struct i40e_rx_queue {
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struct rte_mempool *mp; /**< mbuf pool to populate RX ring */
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volatile union i40e_rx_desc *rx_ring;/**< RX ring virtual address */
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uint64_t rx_ring_phys_addr; /**< RX ring DMA address */
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struct i40e_rx_entry *sw_ring; /**< address of RX soft ring */
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uint16_t nb_rx_desc; /**< number of RX descriptors */
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uint16_t rx_free_thresh; /**< max free RX desc to hold */
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uint16_t rx_tail; /**< current value of tail */
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uint16_t nb_rx_hold; /**< number of held free RX desc */
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struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
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struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
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#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
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uint16_t rx_nb_avail; /**< number of staged packets ready */
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uint16_t rx_next_avail; /**< index of next staged packets */
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uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
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struct rte_mbuf fake_mbuf; /**< dummy mbuf */
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struct rte_mbuf *rx_stage[RTE_PMD_I40E_RX_MAX_BURST * 2];
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#endif
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uint8_t port_id; /**< device port ID */
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uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise */
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uint16_t queue_id; /**< RX queue index */
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uint16_t reg_idx; /**< RX queue register index */
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uint8_t drop_en; /**< if not 0, set register bit */
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volatile uint8_t *qrx_tail; /**< register address of tail */
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struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
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uint16_t rx_buf_len; /* The packet buffer size */
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uint16_t rx_hdr_len; /* The header buffer size */
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uint16_t max_pkt_len; /* Maximum packet length */
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uint8_t hs_mode; /* Header Split mode */
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bool q_set; /**< indicate if rx queue has been configured */
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bool rx_deferred_start; /**< don't start this queue in dev start */
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};
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struct i40e_tx_entry {
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struct rte_mbuf *mbuf;
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uint16_t next_id;
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uint16_t last_id;
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};
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/*
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* Structure associated with each TX queue.
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*/
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struct i40e_tx_queue {
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uint16_t nb_tx_desc; /**< number of TX descriptors */
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uint64_t tx_ring_phys_addr; /**< TX ring DMA address */
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volatile struct i40e_tx_desc *tx_ring; /**< TX ring virtual address */
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struct i40e_tx_entry *sw_ring; /**< virtual address of SW ring */
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uint16_t tx_tail; /**< current value of tail register */
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volatile uint8_t *qtx_tail; /**< register address of tail */
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uint16_t nb_tx_used; /**< number of TX desc used since RS bit set */
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/**< index to last TX descriptor to have been cleaned */
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uint16_t last_desc_cleaned;
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/**< Total number of TX descriptors ready to be allocated. */
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uint16_t nb_tx_free;
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/**< Start freeing TX buffers if there are less free descriptors than
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this value. */
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uint16_t tx_free_thresh;
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/** Number of TX descriptors to use before RS bit is set. */
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uint16_t tx_rs_thresh;
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uint8_t pthresh; /**< Prefetch threshold register. */
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uint8_t hthresh; /**< Host threshold register. */
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uint8_t wthresh; /**< Write-back threshold reg. */
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uint8_t port_id; /**< Device port identifier. */
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uint16_t queue_id; /**< TX queue index. */
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uint16_t reg_idx;
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uint32_t txq_flags;
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struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
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uint16_t tx_next_dd;
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uint16_t tx_next_rs;
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bool q_set; /**< indicate if tx queue has been configured */
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bool tx_deferred_start; /**< don't start this queue in dev start */
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};
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/** Offload features */
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union i40e_tx_offload {
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uint64_t data;
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struct {
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uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
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uint64_t l3_len:9; /**< L3 (IP) Header Length. */
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uint64_t l4_len:8; /**< L4 Header Length. */
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uint64_t tso_segsz:16; /**< TCP TSO segment size */
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uint64_t outer_l2_len:8; /**< outer L2 Header Length */
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uint64_t outer_l3_len:16; /**< outer L3 Header Length */
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};
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};
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int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mp);
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int i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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void i40e_dev_rx_queue_release(void *rxq);
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void i40e_dev_tx_queue_release(void *txq);
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uint16_t i40e_recv_pkts(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t i40e_recv_scattered_pkts(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t i40e_xmit_pkts(void *tx_queue,
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struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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int i40e_tx_queue_init(struct i40e_tx_queue *txq);
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int i40e_rx_queue_init(struct i40e_rx_queue *rxq);
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void i40e_free_tx_resources(struct i40e_tx_queue *txq);
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void i40e_free_rx_resources(struct i40e_rx_queue *rxq);
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void i40e_dev_clear_queues(struct rte_eth_dev *dev);
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void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
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void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
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void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
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int i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);
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void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
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uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
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uint16_t rx_queue_id);
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int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
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#endif /* _I40E_RXTX_H_ */
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