7da29a644c
This patch support copy, submit, completed and completed status functionality of DMA driver. Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
206 lines
5.0 KiB
C
206 lines
5.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2021 NXP
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*/
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#ifndef _DPAA_QDMA_H_
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#define _DPAA_QDMA_H_
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#include <rte_io.h>
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#ifndef BIT
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#define BIT(nr) (1UL << (nr))
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#endif
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#define CORE_NUMBER 4
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#define RETRIES 5
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#ifndef GENMASK
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#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
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#define GENMASK(h, l) \
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(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
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#endif
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#define FSL_QDMA_DMR 0x0
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#define FSL_QDMA_DSR 0x4
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#define FSL_QDMA_DEDR 0xe04
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#define FSL_QDMA_DECFDW0R 0xe10
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#define FSL_QDMA_DECFDW1R 0xe14
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#define FSL_QDMA_DECFDW2R 0xe18
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#define FSL_QDMA_DECFDW3R 0xe1c
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#define FSL_QDMA_DECFQIDR 0xe30
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#define FSL_QDMA_DECBR 0xe34
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#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
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#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x))
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#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
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#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
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#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
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#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
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#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
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#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
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#define FSL_QDMA_SQEDPAR 0x808
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#define FSL_QDMA_SQDPAR 0x80c
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#define FSL_QDMA_SQEEPAR 0x810
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#define FSL_QDMA_SQEPAR 0x814
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#define FSL_QDMA_BSQMR 0x800
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#define FSL_QDMA_BSQSR 0x804
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#define FSL_QDMA_BSQICR 0x828
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#define FSL_QDMA_CQIER 0xa10
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#define FSL_QDMA_SQCCMR 0xa20
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#define FSL_QDMA_SQCCMR_ENTER_WM 0x200000
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#define FSL_QDMA_QUEUE_MAX 8
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#define FSL_QDMA_BCQMR_EN 0x80000000
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#define FSL_QDMA_BCQMR_EI_BE 0x40
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#define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
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#define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
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#define FSL_QDMA_BCQSR_QF_XOFF_BE 0x1000100
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#define FSL_QDMA_BSQMR_EN 0x80000000
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#define FSL_QDMA_BSQMR_DI_BE 0x40
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#define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
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#define FSL_QDMA_BSQSR_QE_BE 0x200
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#define FSL_QDMA_DMR_DQD 0x40000000
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#define FSL_QDMA_DSR_DB 0x80000000
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#define FSL_QDMA_COMMAND_BUFFER_SIZE 64
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#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
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#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
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#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
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#define FSL_QDMA_QUEUE_NUM_MAX 8
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#define FSL_QDMA_CMD_RWTTYPE 0x4
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#define FSL_QDMA_CMD_LWC 0x2
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#define FSL_QDMA_CMD_RWTTYPE_OFFSET 28
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#define FSL_QDMA_CMD_LWC_OFFSET 16
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#define QDMA_CCDF_STATUS 20
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#define QDMA_CCDF_OFFSET 20
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#define QDMA_CCDF_MASK GENMASK(28, 20)
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#define QDMA_CCDF_FOTMAT BIT(29)
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#define QDMA_CCDF_SER BIT(30)
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#define QDMA_SG_FIN BIT(30)
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#define QDMA_SG_LEN_MASK GENMASK(29, 0)
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#define COMMAND_QUEUE_OVERFLOW 10
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/* qdma engine attribute */
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#define QDMA_QUEUE_SIZE 64
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#define QDMA_STATUS_SIZE 64
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#define QDMA_CCSR_BASE 0x8380000
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#define VIRT_CHANNELS 32
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#define QDMA_BLOCK_OFFSET 0x10000
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#define QDMA_BLOCKS 4
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#define QDMA_QUEUES 8
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#define QDMA_DELAY 1000
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#define QDMA_BIG_ENDIAN 1
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#ifdef QDMA_BIG_ENDIAN
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#define QDMA_IN(addr) be32_to_cpu(rte_read32(addr))
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#define QDMA_OUT(addr, val) rte_write32(be32_to_cpu(val), addr)
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#define QDMA_IN_BE(addr) rte_read32(addr)
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#define QDMA_OUT_BE(addr, val) rte_write32(val, addr)
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#else
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#define QDMA_IN(addr) rte_read32(addr)
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#define QDMA_OUT(addr, val) rte_write32(val, addr)
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#define QDMA_IN_BE(addr) be32_to_cpu(rte_write32(addr))
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#define QDMA_OUT_BE(addr, val) rte_write32(be32_to_cpu(val), addr)
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#endif
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#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \
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(((fsl_qdma_engine)->block_offset) * (x))
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typedef void (*dma_call_back)(void *params);
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/* qDMA Command Descriptor Formats */
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struct fsl_qdma_format {
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__le32 status; /* ser, status */
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__le32 cfg; /* format, offset */
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union {
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struct {
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__le32 addr_lo; /* low 32-bits of 40-bit address */
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u8 addr_hi; /* high 8-bits of 40-bit address */
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u8 __reserved1[2];
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u8 cfg8b_w1; /* dd, queue */
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};
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__le64 data;
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};
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};
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/* qDMA Source Descriptor Format */
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struct fsl_qdma_sdf {
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__le32 rev3;
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__le32 cfg; /* rev4, bit[0-11] - ssd, bit[12-23] sss */
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__le32 rev5;
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__le32 cmd;
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};
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/* qDMA Destination Descriptor Format */
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struct fsl_qdma_ddf {
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__le32 rev1;
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__le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */
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__le32 rev3;
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__le32 cmd;
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};
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struct fsl_qdma_chan {
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struct fsl_qdma_engine *qdma;
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struct fsl_qdma_queue *queue;
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bool free;
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struct list_head list;
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};
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struct fsl_qdma_queue {
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struct fsl_qdma_format *virt_head;
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struct list_head comp_used;
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struct list_head comp_free;
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dma_addr_t bus_addr;
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u32 n_cq;
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u32 id;
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u32 count;
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u32 pending;
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struct fsl_qdma_format *cq;
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void *block_base;
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};
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struct fsl_qdma_comp {
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dma_addr_t bus_addr;
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dma_addr_t desc_bus_addr;
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void *virt_addr;
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int index;
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void *desc_virt_addr;
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struct fsl_qdma_chan *qchan;
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dma_call_back call_back_func;
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void *params;
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struct list_head list;
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};
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struct fsl_qdma_engine {
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int desc_allocated;
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void *ctrl_base;
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void *status_base;
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void *block_base;
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u32 n_chans;
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u32 n_queues;
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int error_irq;
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struct fsl_qdma_queue *queue;
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struct fsl_qdma_queue **status;
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struct fsl_qdma_chan *chans;
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u32 num_blocks;
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u8 free_block_id;
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u32 vchan_map[4];
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int block_offset;
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};
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static rte_atomic32_t wait_task[CORE_NUMBER];
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#endif /* _DPAA_QDMA_H_ */
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