7e95c11df4
Add Tx burst multi-segment version for CN9K. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
320 lines
9.0 KiB
C
320 lines
9.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef __CNXK_ETHDEV_H__
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#define __CNXK_ETHDEV_H__
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#include <math.h>
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#include <stdint.h>
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#include <ethdev_driver.h>
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#include <ethdev_pci.h>
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#include <rte_kvargs.h>
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#include <rte_mbuf.h>
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#include <rte_mbuf_pool_ops.h>
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#include <rte_mempool.h>
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#include "roc_api.h"
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#define CNXK_ETH_DEV_PMD_VERSION "1.0"
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/* Used for struct cnxk_eth_dev::flags */
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#define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
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/* VLAN tag inserted by NIX_TX_VTAG_ACTION.
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* In Tx space is always reserved for this in FRS.
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*/
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#define CNXK_NIX_MAX_VTAG_INS 2
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#define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS)
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/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
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#define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
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#define CNXK_NIX_RX_MIN_DESC 16
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#define CNXK_NIX_RX_MIN_DESC_ALIGN 16
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#define CNXK_NIX_RX_NB_SEG_MAX 6
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#define CNXK_NIX_RX_DEFAULT_RING_SZ 4096
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/* Max supported SQB count */
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#define CNXK_NIX_TX_MAX_SQB 512
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/* If PTP is enabled additional SEND MEM DESC is required which
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* takes 2 words, hence max 7 iova address are possible
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*/
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#if defined(RTE_LIBRTE_IEEE1588)
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#define CNXK_NIX_TX_NB_SEG_MAX 7
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#else
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#define CNXK_NIX_TX_NB_SEG_MAX 9
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#endif
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#define CNXK_NIX_TX_MSEG_SG_DWORDS \
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((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \
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CNXK_NIX_TX_NB_SEG_MAX)
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#define CNXK_NIX_RSS_L3_L4_SRC_DST \
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(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \
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ETH_RSS_L4_DST_ONLY)
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#define CNXK_NIX_RSS_OFFLOAD \
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(ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \
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ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
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CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN)
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#define CNXK_NIX_TX_OFFLOAD_CAPA \
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(DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \
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DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \
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DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
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DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \
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DEV_TX_OFFLOAD_IPV4_CKSUM)
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#define CNXK_NIX_RX_OFFLOAD_CAPA \
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(DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \
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DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \
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DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
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DEV_RX_OFFLOAD_RSS_HASH)
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#define RSS_IPV4_ENABLE \
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(ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \
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ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP)
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#define RSS_IPV6_ENABLE \
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(ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \
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ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP)
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#define RSS_IPV6_EX_ENABLE \
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(ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX)
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#define RSS_MAX_LEVELS 3
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#define RSS_IPV4_INDEX 0
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#define RSS_IPV6_INDEX 1
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#define RSS_TCP_INDEX 2
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#define RSS_UDP_INDEX 3
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#define RSS_SCTP_INDEX 4
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#define RSS_DMAC_INDEX 5
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/* Default mark value used when none is provided. */
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#define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff
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#define PTYPE_NON_TUNNEL_WIDTH 16
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#define PTYPE_TUNNEL_WIDTH 12
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#define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH)
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#define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH)
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#define PTYPE_ARRAY_SZ \
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((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t))
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/* Fastpath lookup */
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#define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem"
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#define CNXK_NIX_UDP_TUN_BITMASK \
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((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \
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(1ull << (PKT_TX_TUNNEL_GENEVE >> 45)))
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struct cnxk_eth_qconf {
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union {
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struct rte_eth_txconf tx;
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struct rte_eth_rxconf rx;
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} conf;
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struct rte_mempool *mp;
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uint16_t nb_desc;
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uint8_t valid;
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};
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struct cnxk_eth_dev {
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/* ROC NIX */
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struct roc_nix nix;
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/* ROC RQs, SQs and CQs */
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struct roc_nix_rq *rqs;
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struct roc_nix_sq *sqs;
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struct roc_nix_cq *cqs;
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/* Configured queue count */
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uint16_t nb_rxq;
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uint16_t nb_txq;
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uint8_t configured;
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/* Max macfilter entries */
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uint8_t max_mac_entries;
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uint16_t flags;
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uint8_t ptype_disable;
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bool scalar_ena;
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/* Pointer back to rte */
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struct rte_eth_dev *eth_dev;
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/* HW capabilities / Limitations */
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union {
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struct {
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uint64_t cq_min_4k : 1;
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};
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uint64_t hwcap;
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};
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/* Rx and Tx offload capabilities */
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uint64_t rx_offload_capa;
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uint64_t tx_offload_capa;
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uint32_t speed_capa;
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/* Configured Rx and Tx offloads */
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uint64_t rx_offloads;
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uint64_t tx_offloads;
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/* Platform specific offload flags */
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uint16_t rx_offload_flags;
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uint16_t tx_offload_flags;
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/* ETHDEV RSS HF bitmask */
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uint64_t ethdev_rss_hf;
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/* Saved qconf before lf realloc */
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struct cnxk_eth_qconf *tx_qconf;
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struct cnxk_eth_qconf *rx_qconf;
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/* Rx burst for cleanup(Only Primary) */
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eth_rx_burst_t rx_pkt_burst_no_offload;
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/* Default mac address */
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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/* LSO Tunnel format indices */
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uint64_t lso_tun_fmt;
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};
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struct cnxk_eth_rxq_sp {
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struct cnxk_eth_dev *dev;
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struct cnxk_eth_qconf qconf;
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uint16_t qid;
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} __plt_cache_aligned;
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struct cnxk_eth_txq_sp {
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struct cnxk_eth_dev *dev;
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struct cnxk_eth_qconf qconf;
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uint16_t qid;
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} __plt_cache_aligned;
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static inline struct cnxk_eth_dev *
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cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev)
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{
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return eth_dev->data->dev_private;
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}
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static inline struct cnxk_eth_rxq_sp *
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cnxk_eth_rxq_to_sp(void *__rxq)
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{
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return ((struct cnxk_eth_rxq_sp *)__rxq) - 1;
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}
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static inline struct cnxk_eth_txq_sp *
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cnxk_eth_txq_to_sp(void *__txq)
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{
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return ((struct cnxk_eth_txq_sp *)__txq) - 1;
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}
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/* Common ethdev ops */
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extern struct eth_dev_ops cnxk_eth_dev_ops;
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/* Ops */
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int cnxk_nix_probe(struct rte_pci_driver *pci_drv,
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struct rte_pci_device *pci_dev);
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int cnxk_nix_remove(struct rte_pci_device *pci_dev);
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int cnxk_nix_info_get(struct rte_eth_dev *eth_dev,
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struct rte_eth_dev_info *dev_info);
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int cnxk_nix_configure(struct rte_eth_dev *eth_dev);
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int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
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uint16_t nb_desc, uint16_t fp_tx_q_sz,
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const struct rte_eth_txconf *tx_conf);
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int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
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uint16_t nb_desc, uint16_t fp_rx_q_sz,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mp);
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int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid);
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uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
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/* RSS */
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uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss,
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uint8_t rss_level);
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/* Link */
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void cnxk_eth_dev_link_status_cb(struct roc_nix *nix,
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struct roc_nix_link_info *link);
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int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
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/* Lookup configuration */
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const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev);
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void *cnxk_nix_fastpath_lookup_mem_get(void);
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/* Devargs */
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int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
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struct cnxk_eth_dev *dev);
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/* Inlines */
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static __rte_always_inline uint64_t
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cnxk_pktmbuf_detach(struct rte_mbuf *m)
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{
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struct rte_mempool *mp = m->pool;
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uint32_t mbuf_size, buf_len;
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struct rte_mbuf *md;
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uint16_t priv_size;
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uint16_t refcount;
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/* Update refcount of direct mbuf */
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md = rte_mbuf_from_indirect(m);
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refcount = rte_mbuf_refcnt_update(md, -1);
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priv_size = rte_pktmbuf_priv_size(mp);
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mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);
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buf_len = rte_pktmbuf_data_room_size(mp);
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m->priv_size = priv_size;
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m->buf_addr = (char *)m + mbuf_size;
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m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;
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m->buf_len = (uint16_t)buf_len;
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rte_pktmbuf_reset_headroom(m);
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m->data_len = 0;
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m->ol_flags = 0;
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m->next = NULL;
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m->nb_segs = 1;
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/* Now indirect mbuf is safe to free */
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rte_pktmbuf_free(m);
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if (refcount == 0) {
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rte_mbuf_refcnt_set(md, 1);
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md->data_len = 0;
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md->ol_flags = 0;
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md->next = NULL;
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md->nb_segs = 1;
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return 0;
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} else {
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return 1;
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}
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}
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static __rte_always_inline uint64_t
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cnxk_nix_prefree_seg(struct rte_mbuf *m)
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{
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if (likely(rte_mbuf_refcnt_read(m) == 1)) {
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if (!RTE_MBUF_DIRECT(m))
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return cnxk_pktmbuf_detach(m);
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m->next = NULL;
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m->nb_segs = 1;
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return 0;
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} else if (rte_mbuf_refcnt_update(m, -1) == 0) {
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if (!RTE_MBUF_DIRECT(m))
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return cnxk_pktmbuf_detach(m);
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rte_mbuf_refcnt_set(m, 1);
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m->next = NULL;
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m->nb_segs = 1;
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return 0;
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}
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/* Mbuf is having refcount more than 1 so need not to be freed */
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return 1;
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}
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#endif /* __CNXK_ETHDEV_H__ */
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