80f872ee02
External queue is a queue that has been created and managed outside the PMD. The queues owner might use PMD to generate flow rules using these external queues. When the queue is created in hardware it is given an ID represented by 32 bits. In contrast, the index of the queues in PMD is represented by 16 bits. To enable the use of PMD to generate flow rules, the queue owner must provide a mapping between the HW index and a 16-bit index corresponding to the ethdev API. This patch adds an API enabling to insert/cancel a mapping between HW queue id and ethdev queue id. Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
117 lines
3.5 KiB
C
117 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2020 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_PRIVATE_MLX5_H_
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#define RTE_PMD_PRIVATE_MLX5_H_
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/**
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* @file
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* MLX5 public header.
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*
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* This interface provides the ability to support private PMD
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* dynamic flags.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RTE_PMD_MLX5_FINE_GRANULARITY_INLINE "mlx5_fine_granularity_inline"
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/**
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* Returns the dynamic flags name, that are supported.
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*
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* @param[out] names
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* Array that is used to return the supported dynamic flags names.
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* @param[in] n
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* The number of elements in the names array.
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*
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* @return
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* The number of dynamic flags that were copied if not negative.
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* Otherwise:
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* - ENOMEM - not enough entries in the array
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* - EINVAL - invalid array entry
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*/
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__rte_experimental
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int rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n);
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#define MLX5_DOMAIN_BIT_NIC_RX (1 << 0) /**< NIC RX domain bit mask. */
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#define MLX5_DOMAIN_BIT_NIC_TX (1 << 1) /**< NIC TX domain bit mask. */
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#define MLX5_DOMAIN_BIT_FDB (1 << 2) /**< FDB (TX + RX) domain bit mask. */
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/**
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* Synchronize the flows to make them take effort on hardware.
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* It only supports DR flows now. For DV and Verbs flows, there is no need to
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* call this function, and a success will return directly in case of Verbs.
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*
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* @param[in] port_id
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* The port identifier of the Ethernet device.
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* @param[in] domains
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* Refer to "/usr/include/infiniband/mlx5dv.h".
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* Bitmask of domains in which the synchronization will be done.
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* MLX5_DOMAIN_BIT* macros are used to specify the domains.
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* An ADD or OR operation could be used to synchronize flows in more than
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* one domain per call.
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*
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* @return
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* - (0) if successful.
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* - Negative value if an error.
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*/
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__rte_experimental
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int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains);
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/**
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* External Rx queue rte_flow index minimal value.
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*/
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#define MLX5_EXTERNAL_RX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1)
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/**
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* Update mapping between rte_flow queue index (16 bits) and HW queue index (32
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* bits) for RxQs which is created outside the PMD.
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*
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* @param[in] port_id
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* The port identifier of the Ethernet device.
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* @param[in] dpdk_idx
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* Queue index in rte_flow.
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* @param[in] hw_idx
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* Queue index in hardware.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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* Possible values for rte_errno:
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* - EEXIST - a mapping with the same rte_flow index already exists.
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* - EINVAL - invalid rte_flow index, out of range.
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* - ENODEV - there is no Ethernet device for this port id.
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* - ENOTSUP - the port doesn't support external RxQ.
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*/
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__rte_experimental
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int rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx,
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uint32_t hw_idx);
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/**
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* Remove mapping between rte_flow queue index (16 bits) and HW queue index (32
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* bits) for RxQs which is created outside the PMD.
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*
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* @param[in] port_id
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* The port identifier of the Ethernet device.
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* @param[in] dpdk_idx
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* Queue index in rte_flow.
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*
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* @return
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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* Possible values for rte_errno:
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* - EINVAL - invalid index, out of range, still referenced or doesn't exist.
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* - ENODEV - there is no Ethernet device for this port id.
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* - ENOTSUP - the port doesn't support external RxQ.
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*/
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__rte_experimental
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int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id,
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uint16_t dpdk_idx);
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#ifdef __cplusplus
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}
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#endif
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#endif /* RTE_PMD_PRIVATE_MLX5_H_ */
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