c467608215
HWS matcher resides under the table object, each table can have multiple chained matches with different attributes. Each matcher represents a combination of match and action templates, and can contain multiple configurations based on the templates. Packets are steered from the table to the matcher and from there to other objects. The matcher allows efficient HW packet field matching and action execution based on the configuration done to it. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2022 NVIDIA Corporation & Affiliates
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*/
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#ifndef MLX5DR_MATCHER_H_
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#define MLX5DR_MATCHER_H_
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/* Max supported match template */
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#define MLX5DR_MATCHER_MAX_MT 2
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#define MLX5DR_MATCHER_MAX_MT_ROOT 1
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/* Max supported action template */
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#define MLX5DR_MATCHER_MAX_AT 4
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/* We calculated that concatenating a collision table to the main table with
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* 3% of the main table rows will be enough resources for high insertion
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* success probability.
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*
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* The calculation: log2(2^x * 3 / 100) = log2(2^x) + log2(3/100) = x - 5.05 ~ 5
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*/
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#define MLX5DR_MATCHER_ASSURED_ROW_RATIO 5
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/* Thrashold to determine if amount of rules require a collision table */
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#define MLX5DR_MATCHER_ASSURED_RULES_TH 10
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/* Required depth of an assured collision table */
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#define MLX5DR_MATCHER_ASSURED_COL_TBL_DEPTH 4
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/* Required depth of the main large table */
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#define MLX5DR_MATCHER_ASSURED_MAIN_TBL_DEPTH 2
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struct mlx5dr_match_template {
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struct rte_flow_item *items;
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struct mlx5dr_definer *definer;
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struct mlx5dr_definer_fc *fc;
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uint32_t fc_sz;
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uint64_t item_flags;
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uint8_t vport_item_id;
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enum mlx5dr_match_template_flags flags;
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uint32_t refcount;
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};
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struct mlx5dr_matcher_match_ste {
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struct mlx5dr_pool_chunk ste;
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struct mlx5dr_devx_obj *rtc_0;
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struct mlx5dr_devx_obj *rtc_1;
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struct mlx5dr_pool *pool;
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};
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struct mlx5dr_matcher_action_ste {
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struct mlx5dr_pool_chunk ste;
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struct mlx5dr_pool_chunk stc;
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struct mlx5dr_devx_obj *rtc_0;
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struct mlx5dr_devx_obj *rtc_1;
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struct mlx5dr_pool *pool;
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uint8_t max_stes;
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};
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struct mlx5dr_matcher {
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struct mlx5dr_table *tbl;
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struct mlx5dr_matcher_attr attr;
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struct mlx5dv_flow_matcher *dv_matcher;
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struct mlx5dr_match_template *mt[MLX5DR_MATCHER_MAX_MT];
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uint8_t num_of_mt;
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struct mlx5dr_action_template *at[MLX5DR_MATCHER_MAX_AT];
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uint8_t num_of_at;
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struct mlx5dr_devx_obj *end_ft;
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struct mlx5dr_matcher *col_matcher;
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struct mlx5dr_matcher_match_ste match_ste;
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struct mlx5dr_matcher_action_ste action_ste;
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LIST_ENTRY(mlx5dr_matcher) next;
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};
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int mlx5dr_matcher_conv_items_to_prm(uint64_t *match_buf,
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struct rte_flow_item *items,
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uint8_t *match_criteria,
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bool is_value);
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#endif /* MLX5DR_MATCHER_H_ */
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