30dc028802
ICE choices vector TX path or basic TX path by macro
'ICE_NO_VECTOR_FLAGS'.
This patch adds 'DEV_TX_OFFLOAD_IPV4_CKSUM' in 'ICE_NO_VECTOR_FLAGS'
to make IPv4 checksum offload processed by basic TX path.
Fixes: a224832088
("net/ice: disable TSO offload in vector path")
Cc: stable@dpdk.org
Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
322 lines
7.3 KiB
C
322 lines
7.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation
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*/
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#ifndef _ICE_RXTX_VEC_COMMON_H_
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#define _ICE_RXTX_VEC_COMMON_H_
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#include "ice_rxtx.h"
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static inline uint16_t
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ice_rx_reassemble_packets(struct ice_rx_queue *rxq, struct rte_mbuf **rx_bufs,
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uint16_t nb_bufs, uint8_t *split_flags)
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{
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struct rte_mbuf *pkts[ICE_VPMD_RX_BURST] = {0}; /*finished pkts*/
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struct rte_mbuf *start = rxq->pkt_first_seg;
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struct rte_mbuf *end = rxq->pkt_last_seg;
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unsigned int pkt_idx, buf_idx;
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for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
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if (end) {
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/* processing a split packet */
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end->next = rx_bufs[buf_idx];
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rx_bufs[buf_idx]->data_len += rxq->crc_len;
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start->nb_segs++;
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start->pkt_len += rx_bufs[buf_idx]->data_len;
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end = end->next;
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if (!split_flags[buf_idx]) {
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/* it's the last packet of the set */
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start->hash = end->hash;
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start->vlan_tci = end->vlan_tci;
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start->ol_flags = end->ol_flags;
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/* we need to strip crc for the whole packet */
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start->pkt_len -= rxq->crc_len;
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if (end->data_len > rxq->crc_len) {
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end->data_len -= rxq->crc_len;
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} else {
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/* free up last mbuf */
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struct rte_mbuf *secondlast = start;
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start->nb_segs--;
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while (secondlast->next != end)
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secondlast = secondlast->next;
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secondlast->data_len -= (rxq->crc_len -
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end->data_len);
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secondlast->next = NULL;
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rte_pktmbuf_free_seg(end);
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}
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pkts[pkt_idx++] = start;
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start = NULL;
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end = NULL;
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}
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} else {
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/* not processing a split packet */
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if (!split_flags[buf_idx]) {
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/* not a split packet, save and skip */
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pkts[pkt_idx++] = rx_bufs[buf_idx];
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continue;
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}
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start = rx_bufs[buf_idx];
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end = start;
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rx_bufs[buf_idx]->data_len += rxq->crc_len;
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rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
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}
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}
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/* save the partial packet for next time */
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rxq->pkt_first_seg = start;
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rxq->pkt_last_seg = end;
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rte_memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
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return pkt_idx;
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}
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static __rte_always_inline int
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ice_tx_free_bufs(struct ice_tx_queue *txq)
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{
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struct ice_tx_entry *txep;
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uint32_t n;
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uint32_t i;
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int nb_free = 0;
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struct rte_mbuf *m, *free[ICE_TX_MAX_FREE_BUF_SZ];
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/* check DD bits on threshold descriptor */
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if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
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rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
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rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
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return 0;
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n = txq->tx_rs_thresh;
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/* first buffer to free from S/W ring is at index
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* tx_next_dd - (tx_rs_thresh-1)
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*/
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txep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];
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m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
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if (likely(m)) {
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free[0] = m;
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nb_free = 1;
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for (i = 1; i < n; i++) {
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m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
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if (likely(m)) {
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if (likely(m->pool == free[0]->pool)) {
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free[nb_free++] = m;
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} else {
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rte_mempool_put_bulk(free[0]->pool,
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(void *)free,
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nb_free);
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free[0] = m;
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nb_free = 1;
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}
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}
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}
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rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
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} else {
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for (i = 1; i < n; i++) {
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m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
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if (m)
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rte_mempool_put(m->pool, m);
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}
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}
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/* buffers were freed, update counters */
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txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
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txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
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if (txq->tx_next_dd >= txq->nb_tx_desc)
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txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
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return txq->tx_rs_thresh;
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}
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static __rte_always_inline void
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ice_tx_backlog_entry(struct ice_tx_entry *txep,
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struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
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{
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int i;
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for (i = 0; i < (int)nb_pkts; ++i)
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txep[i].mbuf = tx_pkts[i];
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}
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static inline void
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_ice_rx_queue_release_mbufs_vec(struct ice_rx_queue *rxq)
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{
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const unsigned int mask = rxq->nb_rx_desc - 1;
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unsigned int i;
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if (unlikely(!rxq->sw_ring)) {
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PMD_DRV_LOG(DEBUG, "sw_ring is NULL");
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return;
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}
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if (rxq->rxrearm_nb >= rxq->nb_rx_desc)
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return;
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/* free all mbufs that are valid in the ring */
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if (rxq->rxrearm_nb == 0) {
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for (i = 0; i < rxq->nb_rx_desc; i++) {
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if (rxq->sw_ring[i].mbuf)
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rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
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}
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} else {
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for (i = rxq->rx_tail;
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i != rxq->rxrearm_start;
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i = (i + 1) & mask) {
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if (rxq->sw_ring[i].mbuf)
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rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
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}
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}
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rxq->rxrearm_nb = rxq->nb_rx_desc;
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/* set all entries to NULL */
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memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
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}
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static inline void
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_ice_tx_queue_release_mbufs_vec(struct ice_tx_queue *txq)
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{
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uint16_t i;
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if (unlikely(!txq || !txq->sw_ring)) {
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PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
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return;
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}
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/**
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* vPMD tx will not set sw_ring's mbuf to NULL after free,
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* so need to free remains more carefully.
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*/
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i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
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#ifdef CC_AVX512_SUPPORT
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struct rte_eth_dev *dev = txq->vsi->adapter->eth_dev;
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if (dev->tx_pkt_burst == ice_xmit_pkts_vec_avx512) {
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struct ice_vec_tx_entry *swr = (void *)txq->sw_ring;
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if (txq->tx_tail < i) {
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for (; i < txq->nb_tx_desc; i++) {
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rte_pktmbuf_free_seg(swr[i].mbuf);
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swr[i].mbuf = NULL;
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}
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i = 0;
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}
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for (; i < txq->tx_tail; i++) {
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rte_pktmbuf_free_seg(swr[i].mbuf);
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swr[i].mbuf = NULL;
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}
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} else
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#endif
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{
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if (txq->tx_tail < i) {
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for (; i < txq->nb_tx_desc; i++) {
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rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
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txq->sw_ring[i].mbuf = NULL;
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}
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i = 0;
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}
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for (; i < txq->tx_tail; i++) {
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rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
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txq->sw_ring[i].mbuf = NULL;
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}
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}
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}
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static inline int
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ice_rxq_vec_setup_default(struct ice_rx_queue *rxq)
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{
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uintptr_t p;
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struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
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mb_def.nb_segs = 1;
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mb_def.data_off = RTE_PKTMBUF_HEADROOM;
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mb_def.port = rxq->port_id;
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rte_mbuf_refcnt_set(&mb_def, 1);
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/* prevent compiler reordering: rearm_data covers previous fields */
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rte_compiler_barrier();
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p = (uintptr_t)&mb_def.rearm_data;
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rxq->mbuf_initializer = *(uint64_t *)p;
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return 0;
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}
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static inline int
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ice_rx_vec_queue_default(struct ice_rx_queue *rxq)
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{
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if (!rxq)
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return -1;
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if (!rte_is_power_of_2(rxq->nb_rx_desc))
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return -1;
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if (rxq->rx_free_thresh < ICE_VPMD_RX_BURST)
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return -1;
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if (rxq->nb_rx_desc % rxq->rx_free_thresh)
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return -1;
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if (rxq->proto_xtr != PROTO_XTR_NONE)
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return -1;
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return 0;
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}
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#define ICE_NO_VECTOR_FLAGS ( \
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DEV_TX_OFFLOAD_MULTI_SEGS | \
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DEV_TX_OFFLOAD_VLAN_INSERT | \
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DEV_TX_OFFLOAD_IPV4_CKSUM | \
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DEV_TX_OFFLOAD_SCTP_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_TSO | \
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DEV_TX_OFFLOAD_TCP_CKSUM)
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static inline int
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ice_tx_vec_queue_default(struct ice_tx_queue *txq)
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{
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if (!txq)
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return -1;
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if (txq->offloads & ICE_NO_VECTOR_FLAGS)
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return -1;
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if (txq->tx_rs_thresh < ICE_VPMD_TX_BURST ||
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txq->tx_rs_thresh > ICE_TX_MAX_FREE_BUF_SZ)
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return -1;
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return 0;
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}
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static inline int
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ice_rx_vec_dev_check_default(struct rte_eth_dev *dev)
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{
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int i;
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struct ice_rx_queue *rxq;
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for (i = 0; i < dev->data->nb_rx_queues; i++) {
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rxq = dev->data->rx_queues[i];
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if (ice_rx_vec_queue_default(rxq))
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return -1;
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}
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return 0;
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}
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static inline int
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ice_tx_vec_dev_check_default(struct rte_eth_dev *dev)
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{
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int i;
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struct ice_tx_queue *txq;
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for (i = 0; i < dev->data->nb_tx_queues; i++) {
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txq = dev->data->tx_queues[i];
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if (ice_tx_vec_queue_default(txq))
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return -1;
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}
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return 0;
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}
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#endif
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