05fa3d4a65
Defined FPGA-BUS for Acceleration Drivers of AFUs 1. FPGA PCI Scan (1st Scan) follows DPDK UIO/VFIO PCI Scan Process, probe Intel FPGA Rawdev Driver, it will be covered in following patches. 2. AFU Scan(2nd Scan) bind DPDK driver to FPGA Partial-Bitstream. This scan is trigged by hotplug of IFPGA Rawdev probe, in this scan the AFUs will be created and their drivers are also probed. This patch will introduce rte_afu_device which describe the AFU device listed in the FPGA-BUS. Signed-off-by: Rosen Xu <rosen.xu@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
19 lines
615 B
C
19 lines
615 B
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2018 Intel Corporation
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*/
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#ifndef _IFPGA_COMMON_H_
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#define _IFPGA_COMMON_H_
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int rte_ifpga_get_string_arg(const char *key __rte_unused,
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const char *value, void *extra_args);
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int rte_ifpga_get_integer32_arg(const char *key __rte_unused,
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const char *value, void *extra_args);
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int ifpga_get_integer64_arg(const char *key __rte_unused,
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const char *value, void *extra_args);
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int ifpga_get_unsigned_long(const char *str, int base);
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int ifpga_afu_id_cmp(const struct rte_afu_id *afu_id0,
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const struct rte_afu_id *afu_id1);
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#endif /* _IFPGA_COMMON_H_ */
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