c346551e5e
Signed-off-by: Yong Wang <yongwang@vmware.com> Acked-by: Stephen Hemminger <stephen@networkplumber.org>
176 lines
6.0 KiB
C
176 lines
6.0 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _VMXNET3_ETHDEV_H_
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#define _VMXNET3_ETHDEV_H_
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#define VMXNET3_MAX_MAC_ADDRS 1
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/* UPT feature to negotiate */
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#define VMXNET3_F_RXCSUM 0x0001
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#define VMXNET3_F_RSS 0x0002
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#define VMXNET3_F_RXVLAN 0x0004
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#define VMXNET3_F_LRO 0x0008
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/* Hash Types supported by device */
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#define VMXNET3_RSS_HASH_TYPE_NONE 0x0
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#define VMXNET3_RSS_HASH_TYPE_IPV4 0x01
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#define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02
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#define VMXNET3_RSS_HASH_TYPE_IPV6 0x04
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#define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08
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#define VMXNET3_RSS_HASH_FUNC_NONE 0x0
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#define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01
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#define VMXNET3_RSS_MAX_KEY_SIZE 40
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#define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128
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#define VMXNET3_RSS_OFFLOAD_ALL ( \
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ETH_RSS_IPV4 | \
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ETH_RSS_NONFRAG_IPV4_TCP | \
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ETH_RSS_IPV6 | \
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ETH_RSS_NONFRAG_IPV6_TCP)
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/* RSS configuration structure - shared with device through GPA */
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typedef struct VMXNET3_RSSConf {
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uint16_t hashType;
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uint16_t hashFunc;
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uint16_t hashKeySize;
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uint16_t indTableSize;
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uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE];
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/*
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* indTable is only element that can be changed without
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* device quiesce-reset-update-activation cycle
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*/
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uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];
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} VMXNET3_RSSConf;
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typedef struct vmxnet3_mf_table {
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void *mfTableBase; /* Multicast addresses list */
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uint64_t mfTablePA; /* Physical address of the list */
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uint16_t num_addrs; /* number of multicast addrs */
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} vmxnet3_mf_table_t;
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struct vmxnet3_hw {
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uint8_t *hw_addr0; /* BAR0: PT-Passthrough Regs */
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uint8_t *hw_addr1; /* BAR1: VD-Virtual Device Regs */
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/* BAR2: MSI-X Regs */
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/* BAR3: Port IO */
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void *back;
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uint16_t device_id;
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uint16_t vendor_id;
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uint16_t subsystem_device_id;
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uint16_t subsystem_vendor_id;
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bool adapter_stopped;
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uint8_t perm_addr[ETHER_ADDR_LEN];
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uint8_t num_tx_queues;
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uint8_t num_rx_queues;
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uint8_t bufs_per_pkt;
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Vmxnet3_TxQueueDesc *tqd_start; /* start address of all tx queue desc */
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Vmxnet3_RxQueueDesc *rqd_start; /* start address of all rx queue desc */
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Vmxnet3_DriverShared *shared;
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uint64_t sharedPA;
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uint64_t queueDescPA;
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uint16_t queue_desc_len;
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VMXNET3_RSSConf *rss_conf;
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uint64_t rss_confPA;
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vmxnet3_mf_table_t *mf_table;
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uint32_t shadow_vfta[VMXNET3_VFT_SIZE];
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#define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t))
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};
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#define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg))
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#define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32))
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/* Config space read/writes */
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#define VMXNET3_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
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static inline uint32_t
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vmxnet3_read_addr(volatile void *addr)
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{
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return VMXNET3_PCI_REG(addr);
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}
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#define VMXNET3_PCI_REG_WRITE(reg, value) do { \
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VMXNET3_PCI_REG((reg)) = (value); \
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} while(0)
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#define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
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#define VMXNET3_READ_BAR0_REG(hw, reg) \
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vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))
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#define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \
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VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))
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#define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \
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((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))
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#define VMXNET3_READ_BAR1_REG(hw, reg) \
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vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))
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#define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \
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VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))
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/*
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* RX/TX function prototypes
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*/
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void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);
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void vmxnet3_dev_rx_queue_release(void *rxq);
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void vmxnet3_dev_tx_queue_release(void *txq);
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int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);
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int vmxnet3_rss_configure(struct rte_eth_dev *dev);
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uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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#endif /* _VMXNET3_ETHDEV_H_ */
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