b1b73eaee2
IAVF choices VECTOR TX path or Basic TX path by macro
IAVF_NO_VECTOR_FLAGS. TSO offload only processed by Basic TX path.
Fixes: 605c6f9ca5 ("net/avf: convert to new Rx and Tx offload API")
Cc: stable@dpdk.org
Signed-off-by: Tao Zhu <taox.zhu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
282 lines
9.6 KiB
C
282 lines
9.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Intel Corporation
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*/
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#ifndef _IAVF_RXTX_H_
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#define _IAVF_RXTX_H_
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/* In QLEN must be whole number of 32 descriptors. */
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#define IAVF_ALIGN_RING_DESC 32
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#define IAVF_MIN_RING_DESC 64
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#define IAVF_MAX_RING_DESC 4096
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#define IAVF_DMA_MEM_ALIGN 4096
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/* Base address of the HW descriptor ring should be 128B aligned. */
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#define IAVF_RING_BASE_ALIGN 128
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/* used for Rx Bulk Allocate */
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#define IAVF_RX_MAX_BURST 32
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/* used for Vector PMD */
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#define IAVF_VPMD_RX_MAX_BURST 32
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#define IAVF_VPMD_TX_MAX_BURST 32
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#define IAVF_RXQ_REARM_THRESH 32
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#define IAVF_VPMD_DESCS_PER_LOOP 4
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#define IAVF_VPMD_TX_MAX_FREE_BUF 64
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#define IAVF_NO_VECTOR_FLAGS ( \
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DEV_TX_OFFLOAD_MULTI_SEGS | \
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DEV_TX_OFFLOAD_VLAN_INSERT | \
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DEV_TX_OFFLOAD_SCTP_CKSUM | \
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DEV_TX_OFFLOAD_UDP_CKSUM | \
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DEV_TX_OFFLOAD_TCP_TSO | \
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DEV_TX_OFFLOAD_TCP_CKSUM)
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#define DEFAULT_TX_RS_THRESH 32
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#define DEFAULT_TX_FREE_THRESH 32
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#define IAVF_MIN_TSO_MSS 256
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#define IAVF_MAX_TSO_MSS 9668
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#define IAVF_TSO_MAX_SEG UINT8_MAX
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#define IAVF_TX_MAX_MTU_SEG 8
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#define IAVF_TX_CKSUM_OFFLOAD_MASK ( \
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PKT_TX_IP_CKSUM | \
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PKT_TX_L4_MASK | \
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PKT_TX_TCP_SEG)
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#define IAVF_TX_OFFLOAD_MASK ( \
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PKT_TX_OUTER_IPV6 | \
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PKT_TX_OUTER_IPV4 | \
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PKT_TX_IPV6 | \
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PKT_TX_IPV4 | \
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PKT_TX_VLAN_PKT | \
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PKT_TX_IP_CKSUM | \
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PKT_TX_L4_MASK | \
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PKT_TX_TCP_SEG)
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#define IAVF_TX_OFFLOAD_NOTSUP_MASK \
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(PKT_TX_OFFLOAD_MASK ^ IAVF_TX_OFFLOAD_MASK)
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/* HW desc structure, both 16-byte and 32-byte types are supported */
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#ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
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#define iavf_rx_desc iavf_16byte_rx_desc
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#else
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#define iavf_rx_desc iavf_32byte_rx_desc
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#endif
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struct iavf_rxq_ops {
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void (*release_mbufs)(struct iavf_rx_queue *rxq);
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};
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struct iavf_txq_ops {
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void (*release_mbufs)(struct iavf_tx_queue *txq);
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};
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/* Structure associated with each Rx queue. */
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struct iavf_rx_queue {
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struct rte_mempool *mp; /* mbuf pool to populate Rx ring */
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const struct rte_memzone *mz; /* memzone for Rx ring */
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volatile union iavf_rx_desc *rx_ring; /* Rx ring virtual address */
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uint64_t rx_ring_phys_addr; /* Rx ring DMA address */
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struct rte_mbuf **sw_ring; /* address of SW ring */
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uint16_t nb_rx_desc; /* ring length */
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uint16_t rx_tail; /* current value of tail */
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volatile uint8_t *qrx_tail; /* register address of tail */
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uint16_t rx_free_thresh; /* max free RX desc to hold */
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uint16_t nb_rx_hold; /* number of held free RX desc */
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struct rte_mbuf *pkt_first_seg; /* first segment of current packet */
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struct rte_mbuf *pkt_last_seg; /* last segment of current packet */
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struct rte_mbuf fake_mbuf; /* dummy mbuf */
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/* used for VPMD */
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uint16_t rxrearm_nb; /* number of remaining to be re-armed */
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uint16_t rxrearm_start; /* the idx we start the re-arming from */
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uint64_t mbuf_initializer; /* value to init mbufs */
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/* for rx bulk */
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uint16_t rx_nb_avail; /* number of staged packets ready */
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uint16_t rx_next_avail; /* index of next staged packets */
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uint16_t rx_free_trigger; /* triggers rx buffer allocation */
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struct rte_mbuf *rx_stage[IAVF_RX_MAX_BURST * 2]; /* store mbuf */
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uint16_t port_id; /* device port ID */
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uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
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uint16_t queue_id; /* Rx queue index */
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uint16_t rx_buf_len; /* The packet buffer size */
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uint16_t rx_hdr_len; /* The header buffer size */
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uint16_t max_pkt_len; /* Maximum packet length */
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bool q_set; /* if rx queue has been configured */
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bool rx_deferred_start; /* don't start this queue in dev start */
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const struct iavf_rxq_ops *ops;
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};
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struct iavf_tx_entry {
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struct rte_mbuf *mbuf;
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uint16_t next_id;
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uint16_t last_id;
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};
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/* Structure associated with each TX queue. */
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struct iavf_tx_queue {
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const struct rte_memzone *mz; /* memzone for Tx ring */
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volatile struct iavf_tx_desc *tx_ring; /* Tx ring virtual address */
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uint64_t tx_ring_phys_addr; /* Tx ring DMA address */
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struct iavf_tx_entry *sw_ring; /* address array of SW ring */
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uint16_t nb_tx_desc; /* ring length */
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uint16_t tx_tail; /* current value of tail */
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volatile uint8_t *qtx_tail; /* register address of tail */
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/* number of used desc since RS bit set */
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uint16_t nb_used;
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uint16_t nb_free;
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uint16_t last_desc_cleaned; /* last desc have been cleaned*/
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uint16_t free_thresh;
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uint16_t rs_thresh;
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uint16_t port_id;
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uint16_t queue_id;
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uint64_t offloads;
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uint16_t next_dd; /* next to set RS, for VPMD */
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uint16_t next_rs; /* next to check DD, for VPMD */
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bool q_set; /* if rx queue has been configured */
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bool tx_deferred_start; /* don't start this queue in dev start */
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const struct iavf_txq_ops *ops;
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};
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/* Offload features */
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union iavf_tx_offload {
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uint64_t data;
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struct {
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uint64_t l2_len:7; /* L2 (MAC) Header Length. */
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uint64_t l3_len:9; /* L3 (IP) Header Length. */
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uint64_t l4_len:8; /* L4 Header Length. */
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uint64_t tso_segsz:16; /* TCP TSO segment size */
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/* uint64_t unused : 24; */
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};
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};
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int iavf_dev_rx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mp);
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int iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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void iavf_dev_rx_queue_release(void *rxq);
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int iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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uint16_t nb_desc,
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unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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int iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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void iavf_dev_tx_queue_release(void *txq);
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void iavf_stop_queues(struct rte_eth_dev *dev);
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uint16_t iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_recv_scattered_pkts(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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void iavf_set_rx_function(struct rte_eth_dev *dev);
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void iavf_set_tx_function(struct rte_eth_dev *dev);
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void iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_rxq_info *qinfo);
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void iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
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struct rte_eth_txq_info *qinfo);
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uint32_t iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id);
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int iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset);
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int iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset);
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uint16_t iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_recv_scattered_pkts_vec(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_recv_scattered_pkts_vec_avx2(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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int iavf_rx_vec_dev_check(struct rte_eth_dev *dev);
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int iavf_tx_vec_dev_check(struct rte_eth_dev *dev);
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int iavf_rxq_vec_setup(struct iavf_rx_queue *rxq);
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int iavf_txq_vec_setup(struct iavf_tx_queue *txq);
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static inline
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void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,
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const volatile void *desc,
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uint16_t rx_id)
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{
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#ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
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const volatile union iavf_16byte_rx_desc *rx_desc = desc;
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printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
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rxq->queue_id, rx_id, rx_desc->read.pkt_addr,
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rx_desc->read.hdr_addr);
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#else
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const volatile union iavf_32byte_rx_desc *rx_desc = desc;
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printf("Queue %d Rx_desc %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64
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" QW2: 0x%016"PRIx64" QW3: 0x%016"PRIx64"\n", rxq->queue_id,
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rx_id, rx_desc->read.pkt_addr, rx_desc->read.hdr_addr,
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rx_desc->read.rsvd1, rx_desc->read.rsvd2);
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#endif
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}
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/* All the descriptors are 16 bytes, so just use one of them
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* to print the qwords
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*/
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static inline
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void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
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const volatile void *desc, uint16_t tx_id)
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{
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const char *name;
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const volatile struct iavf_tx_desc *tx_desc = desc;
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enum iavf_tx_desc_dtype_value type;
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type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
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tx_desc->cmd_type_offset_bsz &
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rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
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switch (type) {
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case IAVF_TX_DESC_DTYPE_DATA:
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name = "Tx_data_desc";
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break;
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case IAVF_TX_DESC_DTYPE_CONTEXT:
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name = "Tx_context_desc";
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break;
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default:
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name = "unknown_desc";
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break;
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}
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printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
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txq->queue_id, name, tx_id, tx_desc->buffer_addr,
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tx_desc->cmd_type_offset_bsz);
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}
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#ifdef RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC
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#define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) \
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iavf_dump_rx_descriptor(rxq, desc, rx_id)
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#define IAVF_DUMP_TX_DESC(txq, desc, tx_id) \
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iavf_dump_tx_descriptor(txq, desc, tx_id)
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#else
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#define IAVF_DUMP_RX_DESC(rxq, desc, rx_id) do { } while (0)
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#define IAVF_DUMP_TX_DESC(txq, desc, tx_id) do { } while (0)
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#endif
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#endif /* _IAVF_RXTX_H_ */
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