87dbbdb120
There are some implicit downcast errors in TX offload information
parsing by lgtm tool. This patch is to solve these errors.
Fixes: 64727024d2 ("net/hinic: add device initialization")
Signed-off-by: Ziyang Xuan <xuanziyang2@huawei.com>
145 lines
2.7 KiB
C
145 lines
2.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef _HINIC_PMD_TX_H_
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#define _HINIC_PMD_TX_H_
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#define HINIC_DEFAULT_TX_FREE_THRESH 32
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#define HINIC_MAX_TX_FREE_BULK 64
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#define HINIC_GET_WQ_HEAD(txq) ((txq)->wq->queue_buf_vaddr)
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#define HINIC_GET_WQ_TAIL(txq) \
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((txq)->wq->queue_buf_vaddr + (txq)->wq->wq_buf_size)
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#define HINIC_TX_CKSUM_OFFLOAD_MASK ( \
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PKT_TX_IP_CKSUM | \
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PKT_TX_TCP_CKSUM | \
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PKT_TX_UDP_CKSUM | \
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PKT_TX_SCTP_CKSUM | \
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PKT_TX_OUTER_IP_CKSUM | \
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PKT_TX_TCP_SEG)
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enum sq_wqe_type {
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SQ_NORMAL_WQE = 0,
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};
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/* tx offload info */
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struct hinic_tx_offload_info {
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u8 outer_l2_len;
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u8 outer_l3_type;
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u16 outer_l3_len;
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u8 inner_l2_len;
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u8 inner_l3_type;
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u16 inner_l3_len;
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u8 tunnel_length;
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u8 tunnel_type;
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u8 inner_l4_type;
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u8 inner_l4_len;
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u16 payload_offset;
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u8 inner_l4_tcp_udp;
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u8 rsvd0;
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};
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/* tx sge info */
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struct hinic_wqe_info {
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u16 pi;
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u16 owner;
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u16 around;
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u16 seq_wqebbs;
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u16 sge_cnt;
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u16 cpy_mbuf_cnt;
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};
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struct hinic_sq_ctrl {
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u32 ctrl_fmt;
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u32 queue_info;
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};
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struct hinic_sq_task {
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u32 pkt_info0;
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u32 pkt_info1;
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u32 pkt_info2;
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u32 ufo_v6_identify;
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u32 pkt_info4;
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u32 rsvd5;
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};
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struct hinic_sq_bufdesc {
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struct hinic_sge sge;
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u32 rsvd;
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};
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struct hinic_sq_wqe {
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/* sq wqe control section */
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struct hinic_sq_ctrl ctrl;
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/* sq task control section */
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struct hinic_sq_task task;
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/* sq sge section start address, 1~127 sges */
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struct hinic_sq_bufdesc buf_descs[0];
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};
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struct hinic_txq_stats {
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u64 packets;
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u64 bytes;
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u64 rl_drop;
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u64 tx_busy;
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u64 off_errs;
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u64 cpy_pkts;
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u64 burst_pkts;
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};
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struct hinic_tx_info {
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struct rte_mbuf *mbuf;
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int wqebb_cnt;
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struct rte_mbuf *cpy_mbuf;
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};
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struct hinic_txq {
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/* cacheline0 */
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struct hinic_nic_dev *nic_dev;
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struct hinic_wq *wq;
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struct hinic_sq *sq;
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volatile u16 *cons_idx_addr;
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struct hinic_tx_info *tx_info;
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u16 tx_free_thresh;
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u16 port_id;
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u16 q_id;
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u16 q_depth;
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u32 cos;
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/* cacheline1 */
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struct hinic_txq_stats txq_stats;
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u64 sq_head_addr;
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u64 sq_bot_sge_addr;
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};
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int hinic_setup_tx_resources(struct hinic_txq *txq);
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void hinic_free_all_tx_resources(struct rte_eth_dev *eth_dev);
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void hinic_free_all_tx_mbuf(struct rte_eth_dev *eth_dev);
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void hinic_free_tx_resources(struct hinic_txq *txq);
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u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts);
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void hinic_free_all_tx_skbs(struct hinic_txq *txq);
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void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats);
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void hinic_txq_stats_reset(struct hinic_txq *txq);
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int hinic_create_sq(struct hinic_hwdev *hwdev, u16 q_id, u16 sq_depth);
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void hinic_destroy_sq(struct hinic_hwdev *hwdev, u16 q_id);
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#endif /* _HINIC_PMD_TX_H_ */
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