37d3bde48b
To support auxiliary bus, upgrade the driver to use mlx5 common driver structure. Signed-off-by: Xueming Li <xuemingl@nvidia.com>
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (c) 2021 NVIDIA Corporation & Affiliates
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*/
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#ifndef MLX5_CRYPTO_H_
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#define MLX5_CRYPTO_H_
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#include <stdbool.h>
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#include <rte_cryptodev.h>
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#include <rte_cryptodev_pmd.h>
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#include <mlx5_common_utils.h>
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#include <mlx5_common_devx.h>
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#include <mlx5_common_mr.h>
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#define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)
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#define MLX5_CRYPTO_KEY_LENGTH 80
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struct mlx5_crypto_priv {
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TAILQ_ENTRY(mlx5_crypto_priv) next;
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struct ibv_context *ctx; /* Device context. */
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struct rte_cryptodev *crypto_dev;
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void *uar; /* User Access Region. */
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volatile uint64_t *uar_addr;
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uint32_t pdn; /* Protection Domain number. */
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uint32_t max_segs_num; /* Maximum supported data segs. */
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struct ibv_pd *pd;
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struct mlx5_hlist *dek_hlist; /* Dek hash list. */
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struct rte_cryptodev_config dev_config;
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struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
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struct mlx5_devx_obj *login_obj;
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uint64_t keytag;
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uint16_t wqe_set_size;
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uint16_t umr_wqe_size;
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uint16_t umr_wqe_stride;
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uint16_t max_rdmar_ds;
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#ifndef RTE_ARCH_64
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rte_spinlock_t uar32_sl;
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#endif /* RTE_ARCH_64 */
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};
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struct mlx5_crypto_qp {
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struct mlx5_crypto_priv *priv;
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struct mlx5_devx_cq cq_obj;
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struct mlx5_devx_obj *qp_obj;
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struct rte_cryptodev_stats stats;
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struct mlx5dv_devx_umem *umem_obj;
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void *umem_buf;
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volatile uint32_t *db_rec;
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struct rte_crypto_op **ops;
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struct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */
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struct mlx5_mr_ctrl mr_ctrl;
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uint8_t *wqe;
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uint16_t entries_n;
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uint16_t pi;
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uint16_t ci;
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uint16_t db_pi;
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};
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struct mlx5_crypto_dek {
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struct mlx5_list_entry entry; /* Pointer to DEK hash list entry. */
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struct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */
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uint8_t data[MLX5_CRYPTO_KEY_LENGTH]; /* DEK key data. */
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bool size_is_48; /* Whether the key\data size is 48 bytes or not. */
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} __rte_cache_aligned;
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struct mlx5_crypto_devarg_params {
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bool login_devarg;
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struct mlx5_devx_crypto_login_attr login_attr;
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uint64_t keytag;
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uint32_t max_segs_num;
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};
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int
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mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,
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struct mlx5_crypto_dek *dek);
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struct mlx5_crypto_dek *
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mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,
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struct rte_crypto_cipher_xform *cipher);
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int
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mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);
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void
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mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv);
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#endif /* MLX5_CRYPTO_H_ */
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