241a650061
Patch adds ethdev flow control set/get callback ops, pmd enables modifying flow control attributes like rx_pause, tx_pause, high & low water mark. Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com> Acked-by: Harman Kalra <hkalra@marvell.com>
344 lines
7.9 KiB
C
344 lines
7.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2020 Marvell International Ltd.
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*/
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#include <rte_malloc.h>
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#include "octeontx_ethdev.h"
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#include "octeontx_logs.h"
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#include "octeontx_rxtx.h"
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static int
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octeontx_vlan_hw_filter(struct octeontx_nic *nic, uint8_t flag)
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{
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struct octeontx_vlan_info *vlan = &nic->vlan_info;
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pki_port_vlan_filter_config_t fltr_conf;
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int rc = 0;
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if (vlan->filter_on == flag)
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return rc;
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fltr_conf.port_type = OCTTX_PORT_TYPE_NET;
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fltr_conf.fltr_conf = flag;
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rc = octeontx_pki_port_vlan_fltr_config(nic->port_id, &fltr_conf);
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if (rc != 0) {
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octeontx_log_err("Fail to configure vlan hw filter for port %d",
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nic->port_id);
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goto done;
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}
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vlan->filter_on = flag;
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done:
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return rc;
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}
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int
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octeontx_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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struct rte_eth_rxmode *rxmode;
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int rc = 0;
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rxmode = &dev->data->dev_conf.rxmode;
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if (mask & ETH_VLAN_EXTEND_MASK) {
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octeontx_log_err("Extend offload not supported");
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return -ENOTSUP;
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}
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if (mask & ETH_VLAN_STRIP_MASK) {
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octeontx_log_err("VLAN strip offload not supported");
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return -ENOTSUP;
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}
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if (mask & ETH_VLAN_FILTER_MASK) {
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if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
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rc = octeontx_vlan_hw_filter(nic, true);
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if (rc)
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goto done;
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nic->rx_offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
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nic->rx_offload_flags |= OCCTX_RX_VLAN_FLTR_F;
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} else {
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rc = octeontx_vlan_hw_filter(nic, false);
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if (rc)
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goto done;
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nic->rx_offloads &= ~DEV_RX_OFFLOAD_VLAN_FILTER;
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nic->rx_offload_flags &= ~OCCTX_RX_VLAN_FLTR_F;
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}
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}
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done:
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return rc;
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}
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int
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octeontx_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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struct octeontx_vlan_info *vlan = &nic->vlan_info;
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pki_port_vlan_filter_entry_config_t fltr_entry;
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struct vlan_entry *entry = NULL;
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int entry_count = 0;
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int rc = -EINVAL;
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if (on) {
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TAILQ_FOREACH(entry, &vlan->fltr_tbl, next)
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if (entry->vlan_id == vlan_id) {
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octeontx_log_dbg("Vlan Id is already set");
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return 0;
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}
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} else {
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TAILQ_FOREACH(entry, &vlan->fltr_tbl, next)
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entry_count++;
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if (!entry_count)
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return 0;
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}
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fltr_entry.port_type = OCTTX_PORT_TYPE_NET;
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fltr_entry.vlan_tpid = RTE_ETHER_TYPE_VLAN;
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fltr_entry.vlan_id = vlan_id;
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fltr_entry.entry_conf = on;
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if (on) {
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entry = rte_zmalloc("octeontx_nic_vlan_entry",
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sizeof(struct vlan_entry), 0);
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if (!entry) {
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octeontx_log_err("Failed to allocate memory");
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return -ENOMEM;
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}
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}
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rc = octeontx_pki_port_vlan_fltr_entry_config(nic->port_id,
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&fltr_entry);
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if (rc != 0) {
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octeontx_log_err("Fail to configure vlan filter entry "
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"for port %d", nic->port_id);
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if (entry)
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rte_free(entry);
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goto done;
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}
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if (on) {
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entry->vlan_id = vlan_id;
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TAILQ_INSERT_HEAD(&vlan->fltr_tbl, entry, next);
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} else {
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TAILQ_FOREACH(entry, &vlan->fltr_tbl, next) {
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if (entry->vlan_id == vlan_id) {
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TAILQ_REMOVE(&vlan->fltr_tbl, entry, next);
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rte_free(entry);
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break;
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}
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}
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}
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done:
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return rc;
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}
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int
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octeontx_dev_vlan_offload_init(struct rte_eth_dev *dev)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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int rc;
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TAILQ_INIT(&nic->vlan_info.fltr_tbl);
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rc = octeontx_dev_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
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if (rc)
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octeontx_log_err("Failed to set vlan offload rc=%d", rc);
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return rc;
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}
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int
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octeontx_dev_vlan_offload_fini(struct rte_eth_dev *dev)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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struct octeontx_vlan_info *vlan = &nic->vlan_info;
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pki_port_vlan_filter_entry_config_t fltr_entry;
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struct vlan_entry *entry;
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int rc = 0;
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TAILQ_FOREACH(entry, &vlan->fltr_tbl, next) {
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fltr_entry.port_type = OCTTX_PORT_TYPE_NET;
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fltr_entry.vlan_tpid = RTE_ETHER_TYPE_VLAN;
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fltr_entry.vlan_id = entry->vlan_id;
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fltr_entry.entry_conf = 0;
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rc = octeontx_pki_port_vlan_fltr_entry_config(nic->port_id,
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&fltr_entry);
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if (rc != 0) {
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octeontx_log_err("Fail to configure vlan filter entry "
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"for port %d", nic->port_id);
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break;
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}
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}
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return rc;
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}
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int
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octeontx_dev_set_link_up(struct rte_eth_dev *eth_dev)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);
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int rc, i;
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rc = octeontx_bgx_port_set_link_state(nic->port_id, true);
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if (rc)
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goto done;
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/* Start tx queues */
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for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
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octeontx_dev_tx_queue_start(eth_dev, i);
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done:
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return rc;
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}
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int
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octeontx_dev_set_link_down(struct rte_eth_dev *eth_dev)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);
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int i;
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/* Stop tx queues */
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for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
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octeontx_dev_tx_queue_stop(eth_dev, i);
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return octeontx_bgx_port_set_link_state(nic->port_id, false);
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}
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int
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octeontx_dev_flow_ctrl_get(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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octeontx_mbox_bgx_port_fc_cfg_t conf;
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int rc;
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memset(&conf, 0, sizeof(octeontx_mbox_bgx_port_fc_cfg_t));
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rc = octeontx_bgx_port_flow_ctrl_cfg(nic->port_id, &conf);
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if (rc)
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return rc;
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if (conf.rx_pause && conf.tx_pause)
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fc_conf->mode = RTE_FC_FULL;
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else if (conf.rx_pause)
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fc_conf->mode = RTE_FC_RX_PAUSE;
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else if (conf.tx_pause)
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fc_conf->mode = RTE_FC_TX_PAUSE;
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else
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fc_conf->mode = RTE_FC_NONE;
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/* low_water & high_water values are in Bytes */
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fc_conf->low_water = conf.low_water;
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fc_conf->high_water = conf.high_water;
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return rc;
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}
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int
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octeontx_dev_flow_ctrl_set(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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struct octeontx_fc_info *fc = &nic->fc;
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octeontx_mbox_bgx_port_fc_cfg_t conf;
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uint8_t tx_pause, rx_pause;
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uint16_t max_high_water;
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int rc;
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if (fc_conf->pause_time || fc_conf->mac_ctrl_frame_fwd ||
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fc_conf->autoneg) {
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octeontx_log_err("Below flowctrl parameters are not supported "
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"pause_time, mac_ctrl_frame_fwd and autoneg");
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return -EINVAL;
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}
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if (fc_conf->high_water == fc->high_water &&
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fc_conf->low_water == fc->low_water &&
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fc_conf->mode == fc->mode)
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return 0;
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max_high_water = fc->rx_fifosz - OCTEONTX_BGX_RSVD_RX_FIFOBYTES;
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if (fc_conf->high_water > max_high_water ||
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fc_conf->high_water < fc_conf->low_water) {
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octeontx_log_err("Invalid high/low water values "
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"High_water(in Bytes) must <= 0x%x ",
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max_high_water);
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return -EINVAL;
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}
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if (fc_conf->high_water % BIT(4) || fc_conf->low_water % BIT(4)) {
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octeontx_log_err("High/low water value must be multiple of 16");
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return -EINVAL;
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}
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rx_pause = (fc_conf->mode == RTE_FC_FULL) ||
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(fc_conf->mode == RTE_FC_RX_PAUSE);
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tx_pause = (fc_conf->mode == RTE_FC_FULL) ||
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(fc_conf->mode == RTE_FC_TX_PAUSE);
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conf.high_water = fc_conf->high_water;
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conf.low_water = fc_conf->low_water;
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conf.fc_cfg = BGX_PORT_FC_CFG_SET;
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conf.rx_pause = rx_pause;
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conf.tx_pause = tx_pause;
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rc = octeontx_bgx_port_flow_ctrl_cfg(nic->port_id, &conf);
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if (rc)
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return rc;
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fc->high_water = fc_conf->high_water;
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fc->low_water = fc_conf->low_water;
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fc->mode = fc_conf->mode;
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return rc;
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}
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int
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octeontx_dev_flow_ctrl_init(struct rte_eth_dev *dev)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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struct octeontx_fc_info *fc = &nic->fc;
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struct rte_eth_fc_conf fc_conf;
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int rc;
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rc = octeontx_dev_flow_ctrl_get(dev, &fc_conf);
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if (rc) {
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octeontx_log_err("Failed to get flow control info");
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return rc;
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}
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fc->def_highmark = fc_conf.high_water;
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fc->def_lowmark = fc_conf.low_water;
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fc->def_mode = fc_conf.mode;
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return rc;
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}
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int
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octeontx_dev_flow_ctrl_fini(struct rte_eth_dev *dev)
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{
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struct octeontx_nic *nic = octeontx_pmd_priv(dev);
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struct octeontx_fc_info *fc = &nic->fc;
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struct rte_eth_fc_conf fc_conf;
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memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));
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/* Restore flow control parameters with default values */
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fc_conf.high_water = fc->def_highmark;
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fc_conf.low_water = fc->def_lowmark;
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fc_conf.mode = fc->def_mode;
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return octeontx_dev_flow_ctrl_set(dev, &fc_conf);
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}
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