675e31d877
VXLAN decap offload can happen in stages. The offload request may not come as a single flow request rather may come as two flow offload requests F1 & F2. This patch is adding support for this two stage offload design. The match criteria for F1 is O_DMAC, O_SMAC, O_DST_IP, O_UDP_DPORT and actions are COUNT, MARK, JUMP. The match criteria for F2 is O_SRC_IP, O_DST_IP, VNI and inner header fields. F1 and F2 flow offload requests can come in any order. If F2 flow offload request comes first then F2 can’t be offloaded as there is no O_DMAC information in F2. In this case, F2 will be deferred until F1 flow offload request arrives. When F1 flow offload request is received it will have O_DMAC information. Using F1’s O_DMAC, driver creates an L2 context entry in the hardware as part of offloading F1. F2 will now use F1’s O_DMAC to get the L2 context id associated with this O_DMAC and other flow fields that are cached already at the time of deferring F2 for offloading. F2s that arrive after F1 is offloaded will be directly programmed and not cached. Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2019 Broadcom
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* All rights reserved.
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*/
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#ifndef _BNXT_TF_COMMON_H_
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#define _BNXT_TF_COMMON_H_
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#include <inttypes.h>
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#include "bnxt_ulp.h"
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#include "ulp_template_db_enum.h"
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#define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args)
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#define BNXT_ULP_EM_FLOWS 8192
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#define BNXT_ULP_1M_FLOWS 1000000
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#define BNXT_EEM_RX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1)
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#define BNXT_EEM_TX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1)
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#define BNXT_EEM_HASH_KEY2_USED 0x8000000
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#define BNXT_EEM_RX_HW_HASH_KEY2_BIT BNXT_ULP_1M_FLOWS
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#define BNXT_ULP_DFLT_RX_MAX_KEY 512
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#define BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY 256
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#define BNXT_ULP_DFLT_RX_MEM 0
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#define BNXT_ULP_RX_NUM_FLOWS 32
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#define BNXT_ULP_RX_TBL_IF_ID 0
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#define BNXT_ULP_DFLT_TX_MAX_KEY 512
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#define BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY 256
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#define BNXT_ULP_DFLT_TX_MEM 0
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#define BNXT_ULP_TX_NUM_FLOWS 32
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#define BNXT_ULP_TX_TBL_IF_ID 0
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enum bnxt_tf_rc {
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BNXT_TF_RC_PARSE_ERR = -2,
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BNXT_TF_RC_ERROR = -1,
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BNXT_TF_RC_SUCCESS = 0,
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BNXT_TF_RC_NORMAL = 1,
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BNXT_TF_RC_FID = 2,
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};
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/* eth IPv4 Type */
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enum bnxt_ulp_eth_ip_type {
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BNXT_ULP_ETH_IPV4 = 4,
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BNXT_ULP_ETH_IPV6 = 5,
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BNXT_ULP_MAX_ETH_IP_TYPE = 0
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};
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/* ulp direction Type */
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enum bnxt_ulp_direction_type {
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BNXT_ULP_DIR_INVALID,
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BNXT_ULP_DIR_INGRESS,
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BNXT_ULP_DIR_EGRESS,
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};
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/* enumeration of the interface types */
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enum bnxt_ulp_intf_type {
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BNXT_ULP_INTF_TYPE_INVALID = 0,
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BNXT_ULP_INTF_TYPE_PF,
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BNXT_ULP_INTF_TYPE_TRUSTED_VF,
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BNXT_ULP_INTF_TYPE_VF,
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BNXT_ULP_INTF_TYPE_PF_REP,
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BNXT_ULP_INTF_TYPE_VF_REP,
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BNXT_ULP_INTF_TYPE_PHY_PORT,
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BNXT_ULP_INTF_TYPE_LAST
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};
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struct bnxt_ulp_mark_tbl *
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bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx);
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int32_t
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bnxt_ulp_cntxt_ptr2_mark_db_set(struct bnxt_ulp_context *ulp_ctx,
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struct bnxt_ulp_mark_tbl *mark_tbl);
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#endif /* _BNXT_TF_COMMON_H_ */
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