bd992b2adc
A huge drop in per core MPPS value was observed when PTP stack is
enabled. The reason behind the bottleneck is HW serialises the
transfer of all SQEs, which seeks timestamp capture, on the same
send DMA path. Hence only those packets which requires timestamp
capture should set SETTSTAMP in send mem alg.
With this patch timestamping would be done only for those packets
with PKT_TX_IEEE1588_TMST set.
Fixes: fb3ae0951abd ("net/octeontx2: support Tx")
Fixes: 8980a153006b ("event/octeontx2: support PTP for SSO")
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
413 lines
13 KiB
C
413 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <rte_vect.h>
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#include "otx2_ethdev.h"
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#include "otx2_rx.h"
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#define NIX_DESCS_PER_LOOP 4
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#define CQE_CAST(x) ((struct nix_cqe_hdr_s *)(x))
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#define CQE_SZ(x) ((x) * NIX_CQ_ENTRY_SZ)
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static inline uint16_t
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nix_rx_nb_pkts(struct otx2_eth_rxq *rxq, const uint64_t wdata,
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const uint16_t pkts, const uint32_t qmask)
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{
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uint32_t available = rxq->available;
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/* Update the available count if cached value is not enough */
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if (unlikely(available < pkts)) {
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uint64_t reg, head, tail;
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/* Use LDADDA version to avoid reorder */
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reg = otx2_atomic64_add_sync(wdata, rxq->cq_status);
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/* CQ_OP_STATUS operation error */
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if (reg & BIT_ULL(CQ_OP_STAT_OP_ERR) ||
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reg & BIT_ULL(CQ_OP_STAT_CQ_ERR))
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return 0;
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tail = reg & 0xFFFFF;
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head = (reg >> 20) & 0xFFFFF;
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if (tail < head)
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available = tail - head + qmask + 1;
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else
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available = tail - head;
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rxq->available = available;
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}
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return RTE_MIN(pkts, available);
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}
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static __rte_always_inline uint16_t
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nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t pkts, const uint16_t flags)
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{
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struct otx2_eth_rxq *rxq = rx_queue;
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const uint64_t mbuf_init = rxq->mbuf_initializer;
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const void *lookup_mem = rxq->lookup_mem;
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const uint64_t data_off = rxq->data_off;
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const uintptr_t desc = rxq->desc;
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const uint64_t wdata = rxq->wdata;
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const uint32_t qmask = rxq->qmask;
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uint16_t packets = 0, nb_pkts;
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uint32_t head = rxq->head;
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struct nix_cqe_hdr_s *cq;
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struct rte_mbuf *mbuf;
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nb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);
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while (packets < nb_pkts) {
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/* Prefetch N desc ahead */
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rte_prefetch_non_temporal((void *)(desc + (CQE_SZ(head + 2))));
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cq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head));
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mbuf = nix_get_mbuf_from_cqe(cq, data_off);
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otx2_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init,
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flags);
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otx2_nix_mbuf_to_tstamp(mbuf, rxq->tstamp, flags,
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(uint64_t *)((uint8_t *)mbuf + data_off));
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rx_pkts[packets++] = mbuf;
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otx2_prefetch_store_keep(mbuf);
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head++;
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head &= qmask;
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}
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rxq->head = head;
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rxq->available -= nb_pkts;
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/* Free all the CQs that we've processed */
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otx2_write64((wdata | nb_pkts), rxq->cq_door);
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return nb_pkts;
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}
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#if defined(RTE_ARCH_ARM64)
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static __rte_always_inline uint64_t
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nix_vlan_update(const uint64_t w2, uint64_t ol_flags, uint8x16_t *f)
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{
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if (w2 & BIT_ULL(21) /* vtag0_gone */) {
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ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
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*f = vsetq_lane_u16((uint16_t)(w2 >> 32), *f, 5);
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}
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return ol_flags;
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}
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static __rte_always_inline uint64_t
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nix_qinq_update(const uint64_t w2, uint64_t ol_flags, struct rte_mbuf *mbuf)
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{
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if (w2 & BIT_ULL(23) /* vtag1_gone */) {
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ol_flags |= PKT_RX_QINQ | PKT_RX_QINQ_STRIPPED;
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mbuf->vlan_tci_outer = (uint16_t)(w2 >> 48);
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}
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return ol_flags;
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}
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static __rte_always_inline uint16_t
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nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t pkts, const uint16_t flags)
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{
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struct otx2_eth_rxq *rxq = rx_queue; uint16_t packets = 0;
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uint64x2_t cq0_w8, cq1_w8, cq2_w8, cq3_w8, mbuf01, mbuf23;
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const uint64_t mbuf_initializer = rxq->mbuf_initializer;
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const uint64x2_t data_off = vdupq_n_u64(rxq->data_off);
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uint64_t ol_flags0, ol_flags1, ol_flags2, ol_flags3;
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uint64x2_t rearm0 = vdupq_n_u64(mbuf_initializer);
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uint64x2_t rearm1 = vdupq_n_u64(mbuf_initializer);
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uint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);
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uint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);
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struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;
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const uint16_t *lookup_mem = rxq->lookup_mem;
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const uint32_t qmask = rxq->qmask;
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const uint64_t wdata = rxq->wdata;
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const uintptr_t desc = rxq->desc;
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uint8x16_t f0, f1, f2, f3;
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uint32_t head = rxq->head;
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pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);
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/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */
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pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);
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while (packets < pkts) {
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/* Get the CQ pointers, since the ring size is multiple of
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* 4, We can avoid checking the wrap around of head
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* value after the each access unlike scalar version.
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*/
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const uintptr_t cq0 = desc + CQE_SZ(head);
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/* Prefetch N desc ahead */
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rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(8)));
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rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(9)));
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rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(10)));
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rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(11)));
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/* Get NIX_RX_SG_S for size and buffer pointer */
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cq0_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0) + 64));
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cq1_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1) + 64));
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cq2_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2) + 64));
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cq3_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3) + 64));
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/* Extract mbuf from NIX_RX_SG_S */
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mbuf01 = vzip2q_u64(cq0_w8, cq1_w8);
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mbuf23 = vzip2q_u64(cq2_w8, cq3_w8);
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mbuf01 = vqsubq_u64(mbuf01, data_off);
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mbuf23 = vqsubq_u64(mbuf23, data_off);
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/* Move mbufs to scalar registers for future use */
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mbuf0 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 0);
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mbuf1 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 1);
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mbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0);
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mbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1);
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/* Mask to get packet len from NIX_RX_SG_S */
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const uint8x16_t shuf_msk = {
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0xFF, 0xFF, /* pkt_type set as unknown */
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0xFF, 0xFF, /* pkt_type set as unknown */
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0, 1, /* octet 1~0, low 16 bits pkt_len */
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0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
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0, 1, /* octet 1~0, 16 bits data_len */
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0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF
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};
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/* Form the rx_descriptor_fields1 with pkt_len and data_len */
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f0 = vqtbl1q_u8(cq0_w8, shuf_msk);
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f1 = vqtbl1q_u8(cq1_w8, shuf_msk);
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f2 = vqtbl1q_u8(cq2_w8, shuf_msk);
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f3 = vqtbl1q_u8(cq3_w8, shuf_msk);
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/* Load CQE word0 and word 1 */
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uint64x2_t cq0_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0)));
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uint64x2_t cq1_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1)));
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uint64x2_t cq2_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2)));
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uint64x2_t cq3_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3)));
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if (flags & NIX_RX_OFFLOAD_RSS_F) {
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/* Fill rss in the rx_descriptor_fields1 */
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f0 = vsetq_lane_u32(vgetq_lane_u32(cq0_w0, 0), f0, 3);
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f1 = vsetq_lane_u32(vgetq_lane_u32(cq1_w0, 0), f1, 3);
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f2 = vsetq_lane_u32(vgetq_lane_u32(cq2_w0, 0), f2, 3);
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f3 = vsetq_lane_u32(vgetq_lane_u32(cq3_w0, 0), f3, 3);
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ol_flags0 = PKT_RX_RSS_HASH;
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ol_flags1 = PKT_RX_RSS_HASH;
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ol_flags2 = PKT_RX_RSS_HASH;
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ol_flags3 = PKT_RX_RSS_HASH;
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} else {
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ol_flags0 = 0; ol_flags1 = 0;
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ol_flags2 = 0; ol_flags3 = 0;
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}
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if (flags & NIX_RX_OFFLOAD_PTYPE_F) {
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/* Fill packet_type in the rx_descriptor_fields1 */
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f0 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
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vgetq_lane_u64(cq0_w0, 1)), f0, 0);
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f1 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
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vgetq_lane_u64(cq1_w0, 1)), f1, 0);
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f2 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
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vgetq_lane_u64(cq2_w0, 1)), f2, 0);
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f3 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
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vgetq_lane_u64(cq3_w0, 1)), f3, 0);
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}
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if (flags & NIX_RX_OFFLOAD_CHECKSUM_F) {
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ol_flags0 |= nix_rx_olflags_get(lookup_mem,
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vgetq_lane_u64(cq0_w0, 1));
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ol_flags1 |= nix_rx_olflags_get(lookup_mem,
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vgetq_lane_u64(cq1_w0, 1));
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ol_flags2 |= nix_rx_olflags_get(lookup_mem,
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vgetq_lane_u64(cq2_w0, 1));
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ol_flags3 |= nix_rx_olflags_get(lookup_mem,
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vgetq_lane_u64(cq3_w0, 1));
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}
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if (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) {
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uint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16);
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uint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16);
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uint64_t cq2_w2 = *(uint64_t *)(cq0 + CQE_SZ(2) + 16);
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uint64_t cq3_w2 = *(uint64_t *)(cq0 + CQE_SZ(3) + 16);
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ol_flags0 = nix_vlan_update(cq0_w2, ol_flags0, &f0);
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ol_flags1 = nix_vlan_update(cq1_w2, ol_flags1, &f1);
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ol_flags2 = nix_vlan_update(cq2_w2, ol_flags2, &f2);
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ol_flags3 = nix_vlan_update(cq3_w2, ol_flags3, &f3);
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ol_flags0 = nix_qinq_update(cq0_w2, ol_flags0, mbuf0);
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ol_flags1 = nix_qinq_update(cq1_w2, ol_flags1, mbuf1);
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ol_flags2 = nix_qinq_update(cq2_w2, ol_flags2, mbuf2);
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ol_flags3 = nix_qinq_update(cq3_w2, ol_flags3, mbuf3);
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}
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if (flags & NIX_RX_OFFLOAD_MARK_UPDATE_F) {
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ol_flags0 = nix_update_match_id(*(uint16_t *)
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(cq0 + CQE_SZ(0) + 38), ol_flags0, mbuf0);
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ol_flags1 = nix_update_match_id(*(uint16_t *)
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(cq0 + CQE_SZ(1) + 38), ol_flags1, mbuf1);
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ol_flags2 = nix_update_match_id(*(uint16_t *)
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(cq0 + CQE_SZ(2) + 38), ol_flags2, mbuf2);
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ol_flags3 = nix_update_match_id(*(uint16_t *)
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(cq0 + CQE_SZ(3) + 38), ol_flags3, mbuf3);
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}
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/* Form rearm_data with ol_flags */
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rearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);
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rearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);
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rearm2 = vsetq_lane_u64(ol_flags2, rearm2, 1);
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rearm3 = vsetq_lane_u64(ol_flags3, rearm3, 1);
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/* Update rx_descriptor_fields1 */
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vst1q_u64((uint64_t *)mbuf0->rx_descriptor_fields1, f0);
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vst1q_u64((uint64_t *)mbuf1->rx_descriptor_fields1, f1);
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vst1q_u64((uint64_t *)mbuf2->rx_descriptor_fields1, f2);
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vst1q_u64((uint64_t *)mbuf3->rx_descriptor_fields1, f3);
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/* Update rearm_data */
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vst1q_u64((uint64_t *)mbuf0->rearm_data, rearm0);
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vst1q_u64((uint64_t *)mbuf1->rearm_data, rearm1);
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vst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);
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vst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);
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/* Store the mbufs to rx_pkts */
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vst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);
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vst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);
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/* Prefetch mbufs */
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otx2_prefetch_store_keep(mbuf0);
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otx2_prefetch_store_keep(mbuf1);
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otx2_prefetch_store_keep(mbuf2);
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otx2_prefetch_store_keep(mbuf3);
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/* Mark mempool obj as "get" as it is alloc'ed by NIX */
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__mempool_check_cookies(mbuf0->pool, (void **)&mbuf0, 1, 1);
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__mempool_check_cookies(mbuf1->pool, (void **)&mbuf1, 1, 1);
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__mempool_check_cookies(mbuf2->pool, (void **)&mbuf2, 1, 1);
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__mempool_check_cookies(mbuf3->pool, (void **)&mbuf3, 1, 1);
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/* Advance head pointer and packets */
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head += NIX_DESCS_PER_LOOP; head &= qmask;
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packets += NIX_DESCS_PER_LOOP;
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}
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rxq->head = head;
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rxq->available -= packets;
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rte_cio_wmb();
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/* Free all the CQs that we've processed */
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otx2_write64((rxq->wdata | packets), rxq->cq_door);
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return packets;
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}
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#else
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static inline uint16_t
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nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t pkts, const uint16_t flags)
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{
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RTE_SET_USED(rx_queue);
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RTE_SET_USED(rx_pkts);
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RTE_SET_USED(pkts);
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RTE_SET_USED(flags);
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return 0;
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}
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#endif
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#define R(name, f5, f4, f3, f2, f1, f0, flags) \
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static uint16_t __rte_noinline __hot \
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otx2_nix_recv_pkts_ ## name(void *rx_queue, \
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struct rte_mbuf **rx_pkts, uint16_t pkts) \
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{ \
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return nix_recv_pkts(rx_queue, rx_pkts, pkts, (flags)); \
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} \
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\
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static uint16_t __rte_noinline __hot \
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otx2_nix_recv_pkts_mseg_ ## name(void *rx_queue, \
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struct rte_mbuf **rx_pkts, uint16_t pkts) \
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{ \
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return nix_recv_pkts(rx_queue, rx_pkts, pkts, \
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(flags) | NIX_RX_MULTI_SEG_F); \
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} \
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\
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static uint16_t __rte_noinline __hot \
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otx2_nix_recv_pkts_vec_ ## name(void *rx_queue, \
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struct rte_mbuf **rx_pkts, uint16_t pkts) \
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{ \
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/* TSTMP is not supported by vector */ \
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if ((flags) & NIX_RX_OFFLOAD_TSTAMP_F) \
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return 0; \
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return nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, (flags)); \
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} \
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NIX_RX_FASTPATH_MODES
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#undef R
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static inline void
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pick_rx_func(struct rte_eth_dev *eth_dev,
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const eth_rx_burst_t rx_burst[2][2][2][2][2][2])
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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/* [TSTMP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */
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eth_dev->rx_pkt_burst = rx_burst
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
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[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
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|
[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]
|
|
[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]
|
|
[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];
|
|
}
|
|
|
|
void
|
|
otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
|
|
{
|
|
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
|
|
|
|
const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2] = {
|
|
#define R(name, f5, f4, f3, f2, f1, f0, flags) \
|
|
[f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_ ## name,
|
|
|
|
NIX_RX_FASTPATH_MODES
|
|
#undef R
|
|
};
|
|
|
|
const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2] = {
|
|
#define R(name, f5, f4, f3, f2, f1, f0, flags) \
|
|
[f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_mseg_ ## name,
|
|
|
|
NIX_RX_FASTPATH_MODES
|
|
#undef R
|
|
};
|
|
|
|
const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2] = {
|
|
#define R(name, f5, f4, f3, f2, f1, f0, flags) \
|
|
[f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_vec_ ## name,
|
|
|
|
NIX_RX_FASTPATH_MODES
|
|
#undef R
|
|
};
|
|
|
|
/* For PTP enabled, scalar rx function should be chosen as most of the
|
|
* PTP apps are implemented to rx burst 1 pkt.
|
|
*/
|
|
if (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
|
|
pick_rx_func(eth_dev, nix_eth_rx_burst);
|
|
else
|
|
pick_rx_func(eth_dev, nix_eth_rx_vec_burst);
|
|
|
|
if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
|
|
pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);
|
|
|
|
/* Copy multi seg version with no offload for tear down sequence */
|
|
if (rte_eal_process_type() == RTE_PROC_PRIMARY)
|
|
dev->rx_pkt_burst_no_offload =
|
|
nix_eth_rx_burst_mseg[0][0][0][0][0][0];
|
|
rte_mb();
|
|
}
|