Wenzhuo Lu 8cce758d69 net/e1000/base: avoid packet loss for non-1G ...

To avoid packet loss, Phase Lock Loop (PLL) clock gate time needs to be
increased for non 1G speeds.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

2017-01-17 19:36:48 +01:00

..

crypto

crypto/qat: rework request builder for performance

2016-10-26 14:58:37 +02:00

net

net/e1000/base: avoid packet loss for non-1G

2017-01-17 19:36:48 +01:00

Makefile

mk: fix build dependency of drivers on pmdinfogen

2016-07-08 12:04:02 +02:00