eeded2044a
Let's try to enforce the convention where most drivers use a pmd. logtype
with their class reflected in it, and libraries use a lib. logtype.
Introduce two new macros:
- RTE_LOG_REGISTER_DEFAULT can be used when a single logtype is
used in a component. It is associated to the default name provided
by the build system,
- RTE_LOG_REGISTER_SUFFIX can be used when multiple logtypes are used,
and then the passed name is appended to the default name,
RTE_LOG_REGISTER is left untouched for existing external users
and for components that do not comply with the convention.
There is a new Meson variable log_prefix to adapt the default name
for baseband (pmd.bb.), bus (no pmd.) and mempool (no pmd.) classes.
Note: achieved with below commands + reverted change on net/bonding +
edits on crypto/virtio, compress/mlx5, regex/mlx5
$ git grep -l RTE_LOG_REGISTER drivers/ |
while read file; do
pattern=${file##drivers/};
class=${pattern%%/*};
pattern=${pattern#$class/};
drv=${pattern%%/*};
case "$class" in
baseband) pattern=pmd.bb.$drv;;
bus) pattern=bus.$drv;;
mempool) pattern=mempool.$drv;;
*) pattern=pmd.$class.$drv;;
esac
sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern',/RTE_LOG_REGISTER_DEFAULT(\1,/' $file;
sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern'\.\(.*\),/RTE_LOG_REGISTER_SUFFIX(\1, \2,/' $file;
done
$ git grep -l RTE_LOG_REGISTER lib/ |
while read file; do
pattern=${file##lib/};
pattern=lib.${pattern%%/*};
sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern',/RTE_LOG_REGISTER_DEFAULT(\1,/' $file;
sed -i -e 's/RTE_LOG_REGISTER(\(.*\), '$pattern'\.\(.*\),/RTE_LOG_REGISTER_SUFFIX(\1, \2,/' $file;
done
Signed-off-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
344 lines
7.9 KiB
C
344 lines
7.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017-2020 Intel Corporation
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*/
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#include <stddef.h>
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#include <string.h>
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#include <stdint.h>
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#include <rte_cpuflags.h>
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#include <rte_common.h>
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#include <rte_net_crc.h>
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#include <rte_eal.h>
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#include <rte_log.h>
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#include <rte_vect.h>
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#include "net_crc.h"
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/** CRC polynomials */
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#define CRC32_ETH_POLYNOMIAL 0x04c11db7UL
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#define CRC16_CCITT_POLYNOMIAL 0x1021U
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#define CRC_LUT_SIZE 256
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/* crc tables */
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static uint32_t crc32_eth_lut[CRC_LUT_SIZE];
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static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];
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static uint32_t
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rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len);
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static uint32_t
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rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len);
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static uint32_t
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rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);
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static uint32_t
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rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);
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typedef uint32_t
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(*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);
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static rte_net_crc_handler handlers_default[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_default_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_default_handler,
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};
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static const rte_net_crc_handler *handlers = handlers_default;
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static const rte_net_crc_handler handlers_scalar[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,
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};
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#ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
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static const rte_net_crc_handler handlers_avx512[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_avx512_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_avx512_handler,
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};
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#endif
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#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
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static const rte_net_crc_handler handlers_sse42[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,
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};
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#endif
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#ifdef CC_ARM64_NEON_PMULL_SUPPORT
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static const rte_net_crc_handler handlers_neon[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,
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};
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#endif
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static uint16_t max_simd_bitwidth;
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#define NET_LOG(level, fmt, args...) \
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rte_log(RTE_LOG_ ## level, libnet_logtype, "%s(): " fmt "\n", \
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__func__, ## args)
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RTE_LOG_REGISTER_DEFAULT(libnet_logtype, INFO);
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/* Scalar handling */
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/**
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* Reflect the bits about the middle
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*
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* @param val
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* value to be reflected
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*
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* @return
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* reflected value
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*/
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static uint32_t
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reflect_32bits(uint32_t val)
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{
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uint32_t i, res = 0;
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for (i = 0; i < 32; i++)
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if ((val & (1U << i)) != 0)
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res |= (uint32_t)(1U << (31 - i));
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return res;
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}
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static void
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crc32_eth_init_lut(uint32_t poly,
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uint32_t *lut)
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{
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uint32_t i, j;
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for (i = 0; i < CRC_LUT_SIZE; i++) {
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uint32_t crc = reflect_32bits(i);
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for (j = 0; j < 8; j++) {
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if (crc & 0x80000000L)
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crc = (crc << 1) ^ poly;
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else
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crc <<= 1;
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}
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lut[i] = reflect_32bits(crc);
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}
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}
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static __rte_always_inline uint32_t
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crc32_eth_calc_lut(const uint8_t *data,
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uint32_t data_len,
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uint32_t crc,
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const uint32_t *lut)
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{
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while (data_len--)
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crc = lut[(crc ^ *data++) & 0xffL] ^ (crc >> 8);
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return crc;
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}
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static void
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rte_net_crc_scalar_init(void)
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{
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/* 32-bit crc init */
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crc32_eth_init_lut(CRC32_ETH_POLYNOMIAL, crc32_eth_lut);
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/* 16-bit CRC init */
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crc32_eth_init_lut(CRC16_CCITT_POLYNOMIAL << 16, crc16_ccitt_lut);
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}
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static inline uint32_t
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rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len)
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{
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/* return 16-bit CRC value */
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return (uint16_t)~crc32_eth_calc_lut(data,
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data_len,
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0xffff,
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crc16_ccitt_lut);
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}
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static inline uint32_t
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rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)
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{
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/* return 32-bit CRC value */
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return ~crc32_eth_calc_lut(data,
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data_len,
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0xffffffffUL,
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crc32_eth_lut);
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}
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/* AVX512/VPCLMULQDQ handling */
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#define AVX512_VPCLMULQDQ_CPU_SUPPORTED ( \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) && \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512DQ) && \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ) && \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_VPCLMULQDQ) \
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)
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static const rte_net_crc_handler *
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avx512_vpclmulqdq_get_handlers(void)
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{
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#ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
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if (AVX512_VPCLMULQDQ_CPU_SUPPORTED &&
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max_simd_bitwidth >= RTE_VECT_SIMD_512)
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return handlers_avx512;
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#endif
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NET_LOG(INFO, "Requirements not met, can't use AVX512\n");
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return NULL;
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}
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static void
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avx512_vpclmulqdq_init(void)
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{
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#ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
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if (AVX512_VPCLMULQDQ_CPU_SUPPORTED)
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rte_net_crc_avx512_init();
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#endif
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}
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/* SSE4.2/PCLMULQDQ handling */
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#define SSE42_PCLMULQDQ_CPU_SUPPORTED \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ)
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static const rte_net_crc_handler *
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sse42_pclmulqdq_get_handlers(void)
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{
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#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
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if (SSE42_PCLMULQDQ_CPU_SUPPORTED &&
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max_simd_bitwidth >= RTE_VECT_SIMD_128)
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return handlers_sse42;
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#endif
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NET_LOG(INFO, "Requirements not met, can't use SSE\n");
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return NULL;
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}
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static void
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sse42_pclmulqdq_init(void)
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{
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#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
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if (SSE42_PCLMULQDQ_CPU_SUPPORTED)
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rte_net_crc_sse42_init();
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#endif
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}
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/* NEON/PMULL handling */
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#define NEON_PMULL_CPU_SUPPORTED \
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rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)
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static const rte_net_crc_handler *
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neon_pmull_get_handlers(void)
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{
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#ifdef CC_ARM64_NEON_PMULL_SUPPORT
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if (NEON_PMULL_CPU_SUPPORTED &&
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max_simd_bitwidth >= RTE_VECT_SIMD_128)
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return handlers_neon;
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#endif
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NET_LOG(INFO, "Requirements not met, can't use NEON\n");
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return NULL;
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}
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static void
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neon_pmull_init(void)
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{
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#ifdef CC_ARM64_NEON_PMULL_SUPPORT
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if (NEON_PMULL_CPU_SUPPORTED)
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rte_net_crc_neon_init();
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#endif
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}
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/* Default handling */
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static uint32_t
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rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len)
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{
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handlers = NULL;
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if (max_simd_bitwidth == 0)
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max_simd_bitwidth = rte_vect_get_max_simd_bitwidth();
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handlers = avx512_vpclmulqdq_get_handlers();
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if (handlers != NULL)
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return handlers[RTE_NET_CRC16_CCITT](data, data_len);
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handlers = sse42_pclmulqdq_get_handlers();
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if (handlers != NULL)
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return handlers[RTE_NET_CRC16_CCITT](data, data_len);
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handlers = neon_pmull_get_handlers();
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if (handlers != NULL)
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return handlers[RTE_NET_CRC16_CCITT](data, data_len);
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handlers = handlers_scalar;
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return handlers[RTE_NET_CRC16_CCITT](data, data_len);
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}
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static uint32_t
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rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len)
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{
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handlers = NULL;
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if (max_simd_bitwidth == 0)
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max_simd_bitwidth = rte_vect_get_max_simd_bitwidth();
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handlers = avx512_vpclmulqdq_get_handlers();
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if (handlers != NULL)
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return handlers[RTE_NET_CRC32_ETH](data, data_len);
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handlers = sse42_pclmulqdq_get_handlers();
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if (handlers != NULL)
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return handlers[RTE_NET_CRC32_ETH](data, data_len);
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handlers = neon_pmull_get_handlers();
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if (handlers != NULL)
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return handlers[RTE_NET_CRC32_ETH](data, data_len);
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handlers = handlers_scalar;
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return handlers[RTE_NET_CRC32_ETH](data, data_len);
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}
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/* Public API */
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void
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rte_net_crc_set_alg(enum rte_net_crc_alg alg)
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{
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handlers = NULL;
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if (max_simd_bitwidth == 0)
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max_simd_bitwidth = rte_vect_get_max_simd_bitwidth();
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switch (alg) {
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case RTE_NET_CRC_AVX512:
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handlers = avx512_vpclmulqdq_get_handlers();
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if (handlers != NULL)
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break;
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/* fall-through */
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case RTE_NET_CRC_SSE42:
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handlers = sse42_pclmulqdq_get_handlers();
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break; /* for x86, always break here */
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case RTE_NET_CRC_NEON:
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handlers = neon_pmull_get_handlers();
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/* fall-through */
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case RTE_NET_CRC_SCALAR:
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/* fall-through */
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default:
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break;
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}
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if (handlers == NULL)
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handlers = handlers_scalar;
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}
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uint32_t
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rte_net_crc_calc(const void *data,
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uint32_t data_len,
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enum rte_net_crc_type type)
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{
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uint32_t ret;
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rte_net_crc_handler f_handle;
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f_handle = handlers[type];
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ret = f_handle(data, data_len);
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return ret;
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}
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/* Call initialisation helpers for all crc algorithm handlers */
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RTE_INIT(rte_net_crc_init)
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{
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rte_net_crc_scalar_init();
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sse42_pclmulqdq_init();
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avx512_vpclmulqdq_init();
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neon_pmull_init();
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}
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