4a19f89104
In PAC N3000 card, there is one MAX10 chip in each card, and all of the sensors are connected to MAX10 chip. To support multiple cards in one server, we introducing a sensor device list under intel_max10_device instead of a global list. On the other hand, we using separate intel_max10_device instance for each opae_adatper. Add mutex lock on do_transaction() function for SPI driver to avoid race condition. Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Signed-off-by: Andy Pei <andy.pei@intel.com>
300 lines
6.1 KiB
C
300 lines
6.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2019 Intel Corporation
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*/
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#include "opae_osdep.h"
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#include "opae_spi.h"
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static int nios_spi_indirect_read(struct altera_spi_device *dev, u32 reg,
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u32 *val)
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{
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u64 ctrl = 0;
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u64 stat = 0;
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int loops = SPI_MAX_RETRY;
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ctrl = NIOS_SPI_RD | ((u64)reg << 32);
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opae_writeq(ctrl, dev->regs + NIOS_SPI_CTRL);
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stat = opae_readq(dev->regs + NIOS_SPI_STAT);
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while (!(stat & NIOS_SPI_VALID) && --loops)
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stat = opae_readq(dev->regs + NIOS_SPI_STAT);
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*val = stat & NIOS_SPI_READ_DATA;
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return loops ? 0 : -ETIMEDOUT;
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}
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static int nios_spi_indirect_write(struct altera_spi_device *dev, u32 reg,
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u32 value)
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{
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u64 ctrl = 0;
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u64 stat = 0;
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int loops = SPI_MAX_RETRY;
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ctrl |= NIOS_SPI_WR | (u64)reg << 32;
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ctrl |= value & NIOS_SPI_WRITE_DATA;
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opae_writeq(ctrl, dev->regs + NIOS_SPI_CTRL);
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stat = opae_readq(dev->regs + NIOS_SPI_STAT);
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while (!(stat & NIOS_SPI_VALID) && --loops)
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stat = opae_readq(dev->regs + NIOS_SPI_STAT);
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return loops ? 0 : -ETIMEDOUT;
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}
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static int spi_indirect_write(struct altera_spi_device *dev, u32 reg,
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u32 value)
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{
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u64 ctrl;
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opae_writeq(value & WRITE_DATA_MASK, dev->regs + SPI_WRITE);
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ctrl = CTRL_W | (reg >> 2);
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opae_writeq(ctrl, dev->regs + SPI_CTRL);
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return 0;
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}
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static int spi_indirect_read(struct altera_spi_device *dev, u32 reg,
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u32 *val)
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{
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u64 tmp;
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u64 ctrl;
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ctrl = CTRL_R | (reg >> 2);
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opae_writeq(ctrl, dev->regs + SPI_CTRL);
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/**
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* FIXME: Read one more time to avoid HW timing issue. This is
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* a short term workaround solution, and must be removed once
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* hardware fixing is done.
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*/
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tmp = opae_readq(dev->regs + SPI_READ);
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*val = (u32)tmp;
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return 0;
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}
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int spi_reg_write(struct altera_spi_device *dev, u32 reg,
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u32 value)
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{
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return dev->reg_write(dev, reg, value);
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}
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int spi_reg_read(struct altera_spi_device *dev, u32 reg,
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u32 *val)
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{
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return dev->reg_read(dev, reg, val);
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}
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void spi_cs_activate(struct altera_spi_device *dev, unsigned int chip_select)
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{
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spi_reg_write(dev, ALTERA_SPI_SLAVE_SEL, 1 << chip_select);
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spi_reg_write(dev, ALTERA_SPI_CONTROL, ALTERA_SPI_CONTROL_SSO_MSK);
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}
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void spi_cs_deactivate(struct altera_spi_device *dev)
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{
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spi_reg_write(dev, ALTERA_SPI_CONTROL, 0);
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}
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static int spi_flush_rx(struct altera_spi_device *dev)
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{
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u32 val = 0;
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int ret;
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ret = spi_reg_read(dev, ALTERA_SPI_STATUS, &val);
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if (ret)
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return ret;
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if (val & ALTERA_SPI_STATUS_RRDY_MSK) {
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ret = spi_reg_read(dev, ALTERA_SPI_RXDATA, &val);
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if (ret)
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return ret;
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}
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return 0;
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}
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static unsigned int spi_write_bytes(struct altera_spi_device *dev, int count)
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{
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unsigned int val = 0;
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u16 *p16;
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u32 *p32;
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if (dev->txbuf) {
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switch (dev->data_width) {
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case 1:
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val = dev->txbuf[count];
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break;
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case 2:
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p16 = (u16 *)(dev->txbuf + 2*count);
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val = *p16;
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if (dev->endian == SPI_BIG_ENDIAN)
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val = cpu_to_be16(val);
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break;
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case 4:
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p32 = (u32 *)(dev->txbuf + 4*count);
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val = *p32;
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break;
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}
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}
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return val;
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}
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static void spi_fill_readbuffer(struct altera_spi_device *dev,
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unsigned int value, int count)
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{
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u16 *p16;
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u32 *p32;
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if (dev->rxbuf) {
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switch (dev->data_width) {
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case 1:
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dev->rxbuf[count] = value;
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break;
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case 2:
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p16 = (u16 *)(dev->rxbuf + 2*count);
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if (dev->endian == SPI_BIG_ENDIAN)
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*p16 = cpu_to_be16((u16)value);
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else
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*p16 = (u16)value;
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break;
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case 4:
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p32 = (u32 *)(dev->rxbuf + 4*count);
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if (dev->endian == SPI_BIG_ENDIAN)
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*p32 = cpu_to_be32(value);
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else
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*p32 = value;
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break;
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}
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}
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}
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static int spi_txrx(struct altera_spi_device *dev)
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{
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unsigned int count = 0;
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u32 rxd;
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unsigned int tx_data;
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u32 status;
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int ret;
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while (count < dev->len) {
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tx_data = spi_write_bytes(dev, count);
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spi_reg_write(dev, ALTERA_SPI_TXDATA, tx_data);
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while (1) {
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ret = spi_reg_read(dev, ALTERA_SPI_STATUS, &status);
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if (ret)
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return -EIO;
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if (status & ALTERA_SPI_STATUS_RRDY_MSK)
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break;
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}
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ret = spi_reg_read(dev, ALTERA_SPI_RXDATA, &rxd);
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if (ret)
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return -EIO;
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spi_fill_readbuffer(dev, rxd, count);
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count++;
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}
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return 0;
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}
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int spi_command(struct altera_spi_device *dev, unsigned int chip_select,
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unsigned int wlen, void *wdata,
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unsigned int rlen, void *rdata)
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{
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if (((wlen > 0) && !wdata) || ((rlen > 0) && !rdata)) {
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dev_err(dev, "error on spi command checking\n");
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return -EINVAL;
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}
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wlen = wlen / dev->data_width;
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rlen = rlen / dev->data_width;
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/* flush rx buffer */
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spi_flush_rx(dev);
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spi_cs_activate(dev, chip_select);
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if (wlen) {
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dev->txbuf = wdata;
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dev->rxbuf = rdata;
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dev->len = wlen;
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spi_txrx(dev);
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}
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if (rlen) {
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dev->rxbuf = rdata;
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dev->txbuf = NULL;
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dev->len = rlen;
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spi_txrx(dev);
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}
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spi_cs_deactivate(dev);
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return 0;
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}
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struct altera_spi_device *altera_spi_alloc(void *base, int type)
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{
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struct altera_spi_device *spi_dev =
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opae_malloc(sizeof(struct altera_spi_device));
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if (!spi_dev)
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return NULL;
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spi_dev->regs = base;
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switch (type) {
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case TYPE_SPI:
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spi_dev->reg_read = spi_indirect_read;
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spi_dev->reg_write = spi_indirect_write;
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break;
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case TYPE_NIOS_SPI:
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spi_dev->reg_read = nios_spi_indirect_read;
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spi_dev->reg_write = nios_spi_indirect_write;
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break;
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default:
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dev_err(dev, "%s: invalid SPI type\n", __func__);
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goto error;
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}
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return spi_dev;
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error:
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altera_spi_release(spi_dev);
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return NULL;
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}
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void altera_spi_init(struct altera_spi_device *spi_dev)
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{
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spi_dev->spi_param.info = opae_readq(spi_dev->regs + SPI_CORE_PARAM);
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spi_dev->data_width = spi_dev->spi_param.data_width / 8;
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spi_dev->endian = spi_dev->spi_param.endian;
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spi_dev->num_chipselect = spi_dev->spi_param.num_chipselect;
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dev_info(spi_dev, "spi param: type=%d, data width:%d, endian:%d, clock_polarity=%d, clock=%dMHz, chips=%d, cpha=%d\n",
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spi_dev->spi_param.type,
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spi_dev->data_width, spi_dev->endian,
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spi_dev->spi_param.clock_polarity,
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spi_dev->spi_param.clock,
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spi_dev->num_chipselect,
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spi_dev->spi_param.clock_phase);
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/* clear */
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spi_reg_write(spi_dev, ALTERA_SPI_CONTROL, 0);
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spi_reg_write(spi_dev, ALTERA_SPI_STATUS, 0);
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/* flush rxdata */
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spi_flush_rx(spi_dev);
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}
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void altera_spi_release(struct altera_spi_device *dev)
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{
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if (dev)
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opae_free(dev);
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}
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