c37421a2d6
The number of atomic flows supported was not returned correctly for
DPAA driver. This patch fixes the same.
Fixes: b08dc6430a ("event/dpaa: add queue config get/set")
Cc: stable@dpdk.org
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
80 lines
2.3 KiB
C
80 lines
2.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2017 NXP
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*/
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#ifndef __DPAA_EVENTDEV_H__
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#define __DPAA_EVENTDEV_H__
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#include <rte_eventdev_pmd.h>
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#include <rte_eventdev_pmd_vdev.h>
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#include <rte_atomic.h>
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#include <rte_per_lcore.h>
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#define EVENTDEV_NAME_DPAA_PMD event_dpaa1
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#define DPAA_EVENT_MAX_PORTS 4
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#define DPAA_EVENT_MAX_QUEUES 8
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#define DPAA_EVENT_MIN_DEQUEUE_TIMEOUT 1
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#define DPAA_EVENT_MAX_DEQUEUE_TIMEOUT (UINT32_MAX - 1)
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#define DPAA_EVENT_MAX_QUEUE_FLOWS 2048
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#define DPAA_EVENT_MAX_QUEUE_PRIORITY_LEVELS 8
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#define DPAA_EVENT_MAX_EVENT_PRIORITY_LEVELS 0
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#define DPAA_EVENT_MAX_EVENT_PORT RTE_MIN(RTE_MAX_LCORE, INT8_MAX)
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#define DPAA_EVENT_MAX_PORT_DEQUEUE_DEPTH 8
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#define DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_NS 100000UL
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#define DPAA_EVENT_PORT_DEQUEUE_TIMEOUT_INVALID ((uint64_t)-1)
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#define DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH 1
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#define DPAA_EVENT_MAX_NUM_EVENTS (INT32_MAX - 1)
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#define DPAA_EVENT_DEV_CAP \
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do { \
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RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED | \
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RTE_EVENT_DEV_CAP_BURST_MODE; \
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} while (0)
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#define DPAA_EVENT_QUEUE_ATOMIC_FLOWS 2048
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#define DPAA_EVENT_QUEUE_ORDER_SEQUENCES 2048
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#define RTE_EVENT_ETH_RX_ADAPTER_DPAA_CAP \
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(RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \
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RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \
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RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID)
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#define RTE_EVENT_CRYPTO_ADAPTER_DPAA_CAP \
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(RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW | \
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RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | \
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RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA)
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struct dpaa_eventq {
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/* Channel Id */
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uint16_t ch_id;
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/* Configuration provided by the user */
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uint32_t event_queue_cfg;
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uint32_t event_queue_id;
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/* Event port */
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void *event_port;
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};
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struct dpaa_port {
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struct dpaa_eventq evq_info[DPAA_EVENT_MAX_QUEUES];
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uint8_t num_linked_evq;
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uint8_t is_port_linked;
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uint64_t timeout_us;
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};
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struct dpaa_eventdev {
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struct dpaa_eventq evq_info[DPAA_EVENT_MAX_QUEUES];
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struct dpaa_port ports[DPAA_EVENT_MAX_PORTS];
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uint32_t dequeue_timeout_ns;
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uint32_t nb_events_limit;
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uint8_t max_event_queues;
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uint8_t nb_event_queues;
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uint8_t nb_event_ports;
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uint8_t intr_mode;
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uint32_t nb_event_queue_flows;
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uint32_t nb_event_port_dequeue_depth;
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uint32_t nb_event_port_enqueue_depth;
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uint32_t event_dev_cfg;
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};
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#endif /* __DPAA_EVENTDEV_H__ */
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