59cdf6907b
Add support for setting FEC for a given LMAC. Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
127 lines
4.0 KiB
C
127 lines
4.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef _ROC_BPHY_CGX_H_
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#define _ROC_BPHY_CGX_H_
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#include <pthread.h>
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#include "roc_api.h"
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#define MAX_LMACS_PER_CGX 4
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struct roc_bphy_cgx {
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uint64_t bar0_pa;
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void *bar0_va;
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uint64_t lmac_bmap;
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unsigned int id;
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/* serialize access to the whole structure */
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pthread_mutex_t lock;
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} __plt_cache_aligned;
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enum roc_bphy_cgx_eth_link_speed {
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ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
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ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
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ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
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ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
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ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
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ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
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__ROC_BPHY_CGX_ETH_LINK_SPEED_MAX
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};
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enum roc_bphy_cgx_eth_link_fec {
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ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
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ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
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ROC_BPHY_CGX_ETH_LINK_FEC_RS,
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__ROC_BPHY_CGX_ETH_LINK_FEC_MAX
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};
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enum roc_bphy_cgx_eth_link_mode {
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ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
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ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
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__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
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};
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struct roc_bphy_cgx_link_mode {
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bool full_duplex;
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bool an;
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unsigned int port;
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enum roc_bphy_cgx_eth_link_speed speed;
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enum roc_bphy_cgx_eth_link_mode mode;
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};
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struct roc_bphy_cgx_link_info {
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bool link_up;
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bool full_duplex;
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enum roc_bphy_cgx_eth_link_speed speed;
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bool an;
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enum roc_bphy_cgx_eth_link_fec fec;
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enum roc_bphy_cgx_eth_link_mode mode;
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};
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__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
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__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
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__roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac);
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__roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac);
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__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac, bool state);
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__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac,
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struct roc_bphy_cgx_link_info *info);
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__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac,
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struct roc_bphy_cgx_link_mode *mode);
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__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac);
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__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac);
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__roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac);
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__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac);
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__roc_api int roc_bphy_cgx_fec_set(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac,
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enum roc_bphy_cgx_eth_link_fec fec);
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__roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx,
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unsigned int lmac,
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enum roc_bphy_cgx_eth_link_fec *fec);
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#endif /* _ROC_BPHY_CGX_H_ */
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