c045d2e5cb
Add routines to init, fini, configure & clear CPT device. Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Archana Muniganti <marchana@marvell.com> Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#include <rte_log.h>
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#include "roc_api.h"
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#define PLT_INIT_CB_MAX 8
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static int plt_init_cb_num;
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static roc_plt_init_cb_t plt_init_cbs[PLT_INIT_CB_MAX];
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int
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roc_plt_init_cb_register(roc_plt_init_cb_t cb)
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{
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if (plt_init_cb_num >= PLT_INIT_CB_MAX)
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return -ERANGE;
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plt_init_cbs[plt_init_cb_num++] = cb;
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return 0;
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}
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int
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roc_plt_init(void)
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{
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const struct rte_memzone *mz;
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int i, rc;
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mz = rte_memzone_lookup(PLT_MODEL_MZ_NAME);
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if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
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if (mz == NULL) {
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mz = rte_memzone_reserve(PLT_MODEL_MZ_NAME,
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sizeof(struct roc_model),
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SOCKET_ID_ANY, 0);
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if (mz == NULL) {
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plt_err("Failed to reserve mem for roc_model");
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return -ENOMEM;
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}
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roc_model_init(mz->addr);
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}
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} else {
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if (mz == NULL) {
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plt_err("Failed to lookup mem for roc_model");
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return -ENOMEM;
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}
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roc_model = mz->addr;
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}
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for (i = 0; i < plt_init_cb_num; i++) {
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rc = (*plt_init_cbs[i])();
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if (rc)
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return rc;
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}
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return 0;
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}
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RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_cpt, pmd.crypto.cnxk, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);
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RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);
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