6ad943ff49
Add Intel FPGA Acceleration NIC IPN3KE Flow of PMD driver. Signed-off-by: Rosen Xu <rosen.xu@intel.com> Signed-off-by: Andy Pei <andy.pei@intel.com> Signed-off-by: Dan Wei <dan.wei@intel.com>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2019 Intel Corporation
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*/
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#ifndef _IPN3KE_FLOW_H_
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#define _IPN3KE_FLOW_H_
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/**
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* Expand the length to DWORD alignment with 'Unused' field.
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*
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* FLOW KEY:
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* | Unused |Ruler id (id) | Key1 Key2 … (data) |
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* |--------+---------------+--------------------|
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* | 17bits | 3 bits | Total 108 bits |
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* MSB ---> LSB
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*
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* Note: And the MSb of key data is filled to 0 when it is less
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* than 108 bit.
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*/
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#define IPN3KE_FLOW_KEY_UNUSED_BITS 17
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#define IPN3KE_FLOW_KEY_ID_BITS 3
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#define IPN3KE_FLOW_KEY_DATA_BITS 108
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#define IPN3KE_FLOW_KEY_TOTAL_BITS \
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(IPN3KE_FLOW_KEY_UNUSED_BITS + \
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IPN3KE_FLOW_KEY_ID_BITS + \
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IPN3KE_FLOW_KEY_DATA_BITS)
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#define IPN3KE_FLOW_KEY_ID_OFFSET \
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(IPN3KE_FLOW_KEY_UNUSED_BITS)
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#define IPN3KE_FLOW_KEY_DATA_OFFSET \
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(IPN3KE_FLOW_KEY_ID_OFFSET + IPN3KE_FLOW_KEY_ID_BITS)
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/**
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* Expand the length to DWORD alignment with 'Unused' field.
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*
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* FLOW RESULT:
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* | Unused | enable (acl) | uid |
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* |---------+--------------+--------------|
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* | 15 bits | 1 bit | 16 bits |
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* MSB ---> LSB
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*/
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#define IPN3KE_FLOW_RESULT_UNUSED_BITS 15
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#define IPN3KE_FLOW_RESULT_ACL_BITS 1
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#define IPN3KE_FLOW_RESULT_UID_BITS 16
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#define IPN3KE_FLOW_RESULT_TOTAL_BITS \
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(IPN3KE_FLOW_RESULT_UNUSED_BITS + \
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IPN3KE_FLOW_RESULT_ACL_BITS + \
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IPN3KE_FLOW_RESULT_UID_BITS)
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#define IPN3KE_FLOW_RESULT_ACL_OFFSET \
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(IPN3KE_FLOW_RESULT_UNUSED_BITS)
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#define IPN3KE_FLOW_RESULT_UID_OFFSET \
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(IPN3KE_FLOW_RESULT_ACL_OFFSET + IPN3KE_FLOW_RESULT_ACL_BITS)
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#define IPN3KE_FLOW_RESULT_UID_MAX \
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((1UL << IPN3KE_FLOW_RESULT_UID_BITS) - 1)
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#ifndef BITS_PER_BYTE
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#define BITS_PER_BYTE 8
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#endif
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#define BITS_TO_BYTES(bits) \
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(((bits) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
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struct ipn3ke_flow_rule {
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uint8_t key[BITS_TO_BYTES(IPN3KE_FLOW_KEY_TOTAL_BITS)];
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uint8_t result[BITS_TO_BYTES(IPN3KE_FLOW_RESULT_TOTAL_BITS)];
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};
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struct rte_flow {
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TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
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struct ipn3ke_flow_rule rule;
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};
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TAILQ_HEAD(ipn3ke_flow_list, rte_flow);
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static inline uint16_t ipn3ke_swap16(uint16_t x)
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{
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return ((x & 0xff) << 8) | ((x >> 8) & 0xff);
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}
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static inline uint32_t ipn3ke_swap32(uint32_t x)
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{
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uint32_t high, low;
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uint32_t high1, low1;
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high = (x >> 16) & 0xffff;
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low = x & 0xffff;
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high1 = ipn3ke_swap16(low);
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high1 = high1 << 16;
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low1 = ipn3ke_swap16(high);
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low1 = low1 & 0xffff;
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return high1 | low1;
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}
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extern const struct rte_flow_ops ipn3ke_flow_ops;
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int ipn3ke_flow_init(void *dev);
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#endif /* _IPN3KE_FLOW_H_ */
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